Sync with sys/i386/isa/clock.c revision 1.136.
This commit is contained in:
KATO Takenori
parent
3390b499a2
commit
f0828bf1b0
@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.68 1999/04/28 08:06:00 kato Exp $
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* $Id: clock.c,v 1.69 1999/05/10 09:05:01 kato Exp $
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*/
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/*
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@ -73,6 +73,7 @@
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#include <machine/ipl.h>
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#include <machine/limits.h>
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#include <machine/md_var.h>
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#include <machine/psl.h>
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#if NAPM > 0
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#include <machine/apm_bios.h>
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#include <i386/apm/apm_setup.h>
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@ -92,7 +93,7 @@
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#include <i386/isa/isa_device.h>
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#else
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#include <i386/isa/isa.h>
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#include <i386/isa/rtc.h>
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#include <isa/rtc.h>
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#endif
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#include <i386/isa/timerreg.h>
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@ -137,6 +138,7 @@ static void setup_8254_mixed_mode __P((void));
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#define TIMER0_MAX_FREQ 20000
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int adjkerntz; /* local offset from GMT in seconds */
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int clkintr_pending;
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int disable_rtc_set; /* disable resettodr() if != 0 */
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volatile u_int idelayed;
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int statclock_disable;
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@ -151,6 +153,7 @@ u_int stat_imask = SWI_CLOCK_MASK;
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u_int timer_freq = TIMER_FREQ;
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int timer0_max_count;
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u_int tsc_freq;
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int tsc_is_broken;
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int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
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static int beeping = 0;
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@ -224,24 +227,15 @@ static void
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clkintr(struct clockframe frame)
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{
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if (timecounter->tc_get_timecount == i8254_get_timecount) {
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/*
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* Maintain i8254_offset and related variables. Optimize
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* the usual case where i8254 counter rollover has not been
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* detected in i8254_get_timecount() by pretending that we
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* read the counter when it rolled over. Otherwise, call
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* i8254_get_timecount() to do most of the work. The
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* hardware counter must be read to ensure monotonicity
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* despite multiple rollovers and misbehaving hardware.
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*/
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(disable_intr)(); /* XXX avoid clock locking */
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if (i8254_ticked) {
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i8254_get_timecount(NULL);
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disable_intr();
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if (i8254_ticked)
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i8254_ticked = 0;
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} else {
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else {
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i8254_offset += timer0_max_count;
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i8254_lastcount = 0;
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}
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(enable_intr)(); /* XXX avoid clock locking */
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clkintr_pending = 0;
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enable_intr();
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}
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timer_func(&frame);
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switch (timer0_state) {
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@ -1001,7 +995,7 @@ startrtclock()
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return;
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#endif /* NAPM > 0 */
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if (tsc_present && tsc_freq != 0) {
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if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
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tsc_timecounter.tc_frequency = tsc_freq;
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init_timecounter(&tsc_timecounter);
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}
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@ -1510,13 +1504,21 @@ i8254_get_timecount(struct timecounter *tc)
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low = inb(TIMER_CNTR0);
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high = inb(TIMER_CNTR0);
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count = hardclock_max_count - ((high << 8) | low);
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if (count < i8254_lastcount) {
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count = timer0_max_count - ((high << 8) | low);
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if (count < i8254_lastcount ||
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(!i8254_ticked && (clkintr_pending ||
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((count < 20 || (!(ef & PSL_I) && count < timer0_max_count / 2u)) &&
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#ifdef APIC_IO
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#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */
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/* XXX this assumes that apic_8254_intr is < 24. */
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(lapic_irr1 & (1 << apic_8254_intr))))
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#else
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(inb(IO_ICU1) & 1)))
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#endif
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)) {
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i8254_ticked = 1;
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i8254_offset += hardclock_max_count;
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i8254_offset += timer0_max_count;
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}
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i8254_lastcount = count;
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count += i8254_offset;
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CLOCK_UNLOCK();
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.68 1999/04/28 08:06:00 kato Exp $
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* $Id: clock.c,v 1.69 1999/05/10 09:05:01 kato Exp $
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*/
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/*
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@ -73,6 +73,7 @@
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#include <machine/ipl.h>
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#include <machine/limits.h>
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#include <machine/md_var.h>
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#include <machine/psl.h>
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#if NAPM > 0
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#include <machine/apm_bios.h>
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#include <i386/apm/apm_setup.h>
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@ -92,7 +93,7 @@
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#include <i386/isa/isa_device.h>
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#else
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#include <i386/isa/isa.h>
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#include <i386/isa/rtc.h>
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#include <isa/rtc.h>
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#endif
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#include <i386/isa/timerreg.h>
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@ -137,6 +138,7 @@ static void setup_8254_mixed_mode __P((void));
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#define TIMER0_MAX_FREQ 20000
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int adjkerntz; /* local offset from GMT in seconds */
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int clkintr_pending;
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int disable_rtc_set; /* disable resettodr() if != 0 */
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volatile u_int idelayed;
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int statclock_disable;
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@ -151,6 +153,7 @@ u_int stat_imask = SWI_CLOCK_MASK;
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u_int timer_freq = TIMER_FREQ;
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int timer0_max_count;
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u_int tsc_freq;
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int tsc_is_broken;
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int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
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static int beeping = 0;
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@ -224,24 +227,15 @@ static void
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clkintr(struct clockframe frame)
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{
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if (timecounter->tc_get_timecount == i8254_get_timecount) {
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/*
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* Maintain i8254_offset and related variables. Optimize
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* the usual case where i8254 counter rollover has not been
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* detected in i8254_get_timecount() by pretending that we
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* read the counter when it rolled over. Otherwise, call
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* i8254_get_timecount() to do most of the work. The
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* hardware counter must be read to ensure monotonicity
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* despite multiple rollovers and misbehaving hardware.
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*/
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(disable_intr)(); /* XXX avoid clock locking */
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if (i8254_ticked) {
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i8254_get_timecount(NULL);
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disable_intr();
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if (i8254_ticked)
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i8254_ticked = 0;
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} else {
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else {
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i8254_offset += timer0_max_count;
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i8254_lastcount = 0;
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}
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(enable_intr)(); /* XXX avoid clock locking */
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clkintr_pending = 0;
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enable_intr();
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}
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timer_func(&frame);
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switch (timer0_state) {
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@ -1001,7 +995,7 @@ startrtclock()
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return;
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#endif /* NAPM > 0 */
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if (tsc_present && tsc_freq != 0) {
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if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
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tsc_timecounter.tc_frequency = tsc_freq;
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init_timecounter(&tsc_timecounter);
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}
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@ -1510,13 +1504,21 @@ i8254_get_timecount(struct timecounter *tc)
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low = inb(TIMER_CNTR0);
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high = inb(TIMER_CNTR0);
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count = hardclock_max_count - ((high << 8) | low);
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if (count < i8254_lastcount) {
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count = timer0_max_count - ((high << 8) | low);
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if (count < i8254_lastcount ||
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(!i8254_ticked && (clkintr_pending ||
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((count < 20 || (!(ef & PSL_I) && count < timer0_max_count / 2u)) &&
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#ifdef APIC_IO
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#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */
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/* XXX this assumes that apic_8254_intr is < 24. */
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(lapic_irr1 & (1 << apic_8254_intr))))
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#else
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(inb(IO_ICU1) & 1)))
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#endif
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)) {
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i8254_ticked = 1;
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i8254_offset += hardclock_max_count;
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i8254_offset += timer0_max_count;
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}
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i8254_lastcount = count;
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count += i8254_offset;
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CLOCK_UNLOCK();
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.68 1999/04/28 08:06:00 kato Exp $
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* $Id: clock.c,v 1.69 1999/05/10 09:05:01 kato Exp $
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*/
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/*
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@ -73,6 +73,7 @@
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#include <machine/ipl.h>
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#include <machine/limits.h>
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#include <machine/md_var.h>
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#include <machine/psl.h>
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#if NAPM > 0
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#include <machine/apm_bios.h>
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#include <i386/apm/apm_setup.h>
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@ -92,7 +93,7 @@
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#include <i386/isa/isa_device.h>
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#else
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#include <i386/isa/isa.h>
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#include <i386/isa/rtc.h>
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#include <isa/rtc.h>
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#endif
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#include <i386/isa/timerreg.h>
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@ -137,6 +138,7 @@ static void setup_8254_mixed_mode __P((void));
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#define TIMER0_MAX_FREQ 20000
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int adjkerntz; /* local offset from GMT in seconds */
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int clkintr_pending;
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int disable_rtc_set; /* disable resettodr() if != 0 */
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volatile u_int idelayed;
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int statclock_disable;
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@ -151,6 +153,7 @@ u_int stat_imask = SWI_CLOCK_MASK;
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u_int timer_freq = TIMER_FREQ;
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int timer0_max_count;
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u_int tsc_freq;
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int tsc_is_broken;
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int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
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static int beeping = 0;
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@ -224,24 +227,15 @@ static void
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clkintr(struct clockframe frame)
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{
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if (timecounter->tc_get_timecount == i8254_get_timecount) {
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/*
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* Maintain i8254_offset and related variables. Optimize
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* the usual case where i8254 counter rollover has not been
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* detected in i8254_get_timecount() by pretending that we
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* read the counter when it rolled over. Otherwise, call
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* i8254_get_timecount() to do most of the work. The
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* hardware counter must be read to ensure monotonicity
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* despite multiple rollovers and misbehaving hardware.
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*/
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(disable_intr)(); /* XXX avoid clock locking */
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if (i8254_ticked) {
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i8254_get_timecount(NULL);
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disable_intr();
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if (i8254_ticked)
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i8254_ticked = 0;
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} else {
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else {
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i8254_offset += timer0_max_count;
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i8254_lastcount = 0;
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}
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(enable_intr)(); /* XXX avoid clock locking */
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clkintr_pending = 0;
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enable_intr();
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}
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timer_func(&frame);
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switch (timer0_state) {
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@ -1001,7 +995,7 @@ startrtclock()
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return;
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#endif /* NAPM > 0 */
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if (tsc_present && tsc_freq != 0) {
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if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
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tsc_timecounter.tc_frequency = tsc_freq;
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init_timecounter(&tsc_timecounter);
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}
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@ -1510,13 +1504,21 @@ i8254_get_timecount(struct timecounter *tc)
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low = inb(TIMER_CNTR0);
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high = inb(TIMER_CNTR0);
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count = hardclock_max_count - ((high << 8) | low);
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if (count < i8254_lastcount) {
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count = timer0_max_count - ((high << 8) | low);
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if (count < i8254_lastcount ||
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(!i8254_ticked && (clkintr_pending ||
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((count < 20 || (!(ef & PSL_I) && count < timer0_max_count / 2u)) &&
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#ifdef APIC_IO
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#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */
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/* XXX this assumes that apic_8254_intr is < 24. */
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(lapic_irr1 & (1 << apic_8254_intr))))
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#else
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(inb(IO_ICU1) & 1)))
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#endif
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)) {
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i8254_ticked = 1;
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i8254_offset += hardclock_max_count;
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i8254_offset += timer0_max_count;
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}
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i8254_lastcount = count;
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count += i8254_offset;
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CLOCK_UNLOCK();
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