sdhci_fsl_fdt.c: Add a missing call to mmc_fdt_parse.
Add a missing call to mmc_fdt_parse, without it some dts properties are not parsed. Submitted by: Lukasz Hajec <lha@semihalf.com> Reviewed by: manu Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D30122
This commit is contained in:
Marcin Wojtas
parent
ffd61af32c
commit
f0a9d7d799
@ -45,6 +45,7 @@ __FBSDID("$FreeBSD$");
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#include <dev/extres/clk/clk.h>
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#include <dev/mmc/bridge.h>
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#include <dev/mmc/mmcbrvar.h>
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#include <dev/mmc/mmc_fdt_helpers.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/sdhci/sdhci.h>
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@ -96,11 +97,13 @@ struct sdhci_fsl_fdt_softc {
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struct resource *irq_res;
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void *irq_cookie;
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uint32_t baseclk_hz;
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uint32_t maxclk_hz;
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struct sdhci_fdt_gpio *gpio;
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struct sdhci_slot slot;
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bool slot_init_done;
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uint32_t cmd_and_mode;
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uint16_t sdclk_bits;
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struct mmc_fdt_helper fdt_helper;
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uint32_t (* read)(struct sdhci_fsl_fdt_softc *, bus_size_t);
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void (* write)(struct sdhci_fsl_fdt_softc *, bus_size_t, uint32_t);
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@ -194,9 +197,9 @@ fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc *sc, uint16_t val)
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((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) <<
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SDHCI_DIVIDER_MASK_LEN;
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if (div == 0)
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freq = sc->baseclk_hz;
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freq = sc->maxclk_hz;
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else
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freq = sc->baseclk_hz / (2 * div);
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freq = sc->maxclk_hz / (2 * div);
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for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16); )
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prescale <<= 1;
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@ -445,6 +448,86 @@ sdhci_fsl_fdt_irq(void *arg)
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return;
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}
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static int
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sdhci_fsl_fdt_update_ios(device_t brdev, device_t reqdev)
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{
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int err;
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struct sdhci_fsl_fdt_softc *sc;
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struct mmc_ios *ios;
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struct sdhci_slot *slot;
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err = sdhci_generic_update_ios(brdev, reqdev);
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if (err != 0)
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return (err);
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sc = device_get_softc(brdev);
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slot = device_get_ivars(reqdev);
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ios = &slot->host.ios;
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switch (ios->power_mode) {
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case power_on:
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break;
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case power_off:
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if (bootverbose)
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device_printf(sc->dev, "Powering down sd/mmc\n");
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if (sc->fdt_helper.vmmc_supply)
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regulator_disable(sc->fdt_helper.vmmc_supply);
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if (sc->fdt_helper.vqmmc_supply)
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regulator_disable(sc->fdt_helper.vqmmc_supply);
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break;
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case power_up:
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if (bootverbose)
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device_printf(sc->dev, "Powering up sd/mmc\n");
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if (sc->fdt_helper.vmmc_supply)
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regulator_enable(sc->fdt_helper.vmmc_supply);
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if (sc->fdt_helper.vqmmc_supply)
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regulator_enable(sc->fdt_helper.vqmmc_supply);
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break;
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};
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return (0);
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}
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static int
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sdhci_fsl_fdt_switch_vccq(device_t brdev, device_t reqdev)
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{
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struct sdhci_fsl_fdt_softc *sc;
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struct sdhci_slot *slot;
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int uvolt, err;
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err = sdhci_generic_switch_vccq(brdev, reqdev);
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if (err != 0)
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return (err);
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sc = device_get_softc(brdev);
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if (sc->fdt_helper.vqmmc_supply == NULL)
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return EOPNOTSUPP;
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slot = device_get_ivars(reqdev);
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switch (slot->host.ios.vccq) {
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case vccq_180:
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uvolt = 1800000;
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break;
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case vccq_330:
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uvolt = 3300000;
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break;
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default:
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return EINVAL;
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}
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err = regulator_set_voltage(sc->fdt_helper.vqmmc_supply, uvolt, uvolt);
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if (err != 0) {
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device_printf(sc->dev,
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"Cannot set vqmmc to %d<->%d\n", uvolt, uvolt);
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return (err);
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}
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return (0);
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}
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static int
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sdhci_fsl_fdt_get_ro(device_t bus, device_t child)
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{
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@ -463,10 +546,24 @@ sdhci_fsl_fdt_get_card_present(device_t dev, struct sdhci_slot *slot)
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return (sdhci_fdt_gpio_get_present(sc->gpio));
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}
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static void
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sdhci_fsl_fdt_of_parse(device_t dev)
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{
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struct sdhci_fsl_fdt_softc *sc;
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phandle_t node;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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/* Call mmc_fdt_parse in order to get mmc related properties. */
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mmc_fdt_parse(dev, node, &sc->fdt_helper, &sc->slot.host);
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}
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static int
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sdhci_fsl_fdt_attach(device_t dev)
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{
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struct sdhci_fsl_fdt_softc *sc;
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struct mmc_host *host;
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uint32_t val, buf_order;
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uintptr_t ocd_data;
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uint64_t clk_hz;
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@ -481,6 +578,7 @@ sdhci_fsl_fdt_attach(device_t dev)
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sc->soc_data = (struct sdhci_fsl_fdt_soc_data *)ocd_data;
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sc->dev = dev;
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sc->slot.quirks = sc->soc_data->quirks;
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host = &sc->slot.host;
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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@ -534,6 +632,9 @@ sdhci_fsl_fdt_attach(device_t dev)
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buf_order = SDHCI_FSL_PROT_CTRL_BYTE_SWAP;
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}
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sdhci_fsl_fdt_of_parse(dev);
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sc->maxclk_hz = host->f_max ? host->f_max : sc->baseclk_hz;
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/*
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* Setting this register affects byte order in SDHCI_BUFFER only.
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* If the eSDHC block is connected over a big-endian bus, the data
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@ -555,7 +656,7 @@ sdhci_fsl_fdt_attach(device_t dev)
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WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN);
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val = RD4(sc, SDHCI_FSL_ESDHC_CTRL);
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WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2);
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sc->slot.max_clk = sc->baseclk_hz;
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sc->slot.max_clk = sc->maxclk_hz;
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sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
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/*
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@ -656,11 +757,12 @@ static const device_method_t sdhci_fsl_fdt_methods[] = {
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DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
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/* MMC bridge interface. */
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DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
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DEVMETHOD(mmcbr_request, sdhci_generic_request),
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DEVMETHOD(mmcbr_get_ro, sdhci_fsl_fdt_get_ro),
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DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
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DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
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DEVMETHOD(mmcbr_switch_vccq, sdhci_fsl_fdt_switch_vccq),
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DEVMETHOD(mmcbr_update_ios, sdhci_fsl_fdt_update_ios),
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/* SDHCI accessors. */
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DEVMETHOD(sdhci_read_1, sdhci_fsl_fdt_read_1),
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