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Add Qlogic 10Gigabit Ethernet & CNA Adapter Driver Version 3.10.10 for

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QLogic 8300 Series Adapters

Submitted by: David C Somayajulu (davidcs@freebsd.org) QLogic Corporation
Approved by: George Neville-Neil (gnn@freebsd.org)
This commit is contained in:
David C Somayajulu 2013-05-15 17:03:09 +00:00
parent 2afea814ac
commit f10a77bb82
22 changed files with 11633 additions and 0 deletions
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3
share/man/man4/Makefile
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@ -371,6 +371,7 @@ MAN= aac.4 \
pty.4 \
puc.4 \
${_qlxgb.4} \
${_qlxgbe.4} \
ral.4 \
random.4 \
rc.4 \
@ -791,9 +792,11 @@ _if_ntb.4= if_ntb.4
_ntb.4= ntb.4
_ntb_hw.4= ntb_hw.4
_qlxgb.4= qlxgb.4
_qlxgbe.4= qlxgbe.4
_sfxge.4= sfxge.4
MLINKS+=qlxgb.4 if_qlxgb.4
MLINKS+=qlxgbe.4 if_qlxgbe.4
MLINKS+=sfxge.4 if_sfxge.4
.endif

91
share/man/man4/qlxgbe.4 Normal file
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@ -0,0 +1,91 @@
.\"-
.\" Copyright (c) 2013 Qlogic Corportaion
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd April 1, 2013
.Dt QLXGBE 4
.Os
.Sh NAME
.Nm qlxgbe
.Nd "QLogic 10 Gigabit Ethernet & CNA Adapter Driver"
.Sh SYNOPSIS
To compile this driver into the kernel,
place the following lines in your
kernel configuration file:
.Bd -ragged -offset indent
.Cd "device qlxgbe"
.Ed
.Pp
To load the driver as a
module at boot time, place the following line in
.Xr loader.conf 5 :
.Bd -literal -offset indent
if_qlxgbe_load="YES"
.Ed
.Sh DESCRIPTION
The
.Nm
driver supports IPv4 checksum offload,
TCP and UDP checksum offload for both IPv4 and IPv6,
Large Segment Offload for both IPv4 and IPv6,
Jumbo frames, VLAN Tag, and
Receive Side scaling.
For further hardware information, see
.Pa http://www.qlogic.com/ .
.Sh HARDWARE
The
.Nm
driver supports 10 Gigabit Ethernet & CNA Adapter based on the following
chipsets:
.Pp
.Bl -bullet -compact
.It
QLogic 8300 series
.El
.Sh SUPPORT
For support questions please contact your QLogic approved reseller or
QLogic Technical Support at
.Pa http://support.qlogic.com ,
or by E-mail at
.Aq support@qlogic.com .
.Sh SEE ALSO
.Xr altq 4 ,
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ng_ether 4 ,
.Xr ifconfig 8
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 10.0 .
.Sh AUTHORS
.An -nosplit
The
.Nm
driver was written by
.An David C Somayajulu
at QLogic Corporation.

7
sys/conf/files.amd64
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@ -232,6 +232,13 @@ dev/qlxgb/qla_ioctl.c optional qlxgb pci
dev/qlxgb/qla_isr.c optional qlxgb pci
dev/qlxgb/qla_misc.c optional qlxgb pci
dev/qlxgb/qla_os.c optional qlxgb pci
dev/qlxgbe/ql_dbg.c optional qlxgbe pci
dev/qlxgbe/ql_hw.c optional qlxgbe pci
dev/qlxgbe/ql_ioctl.c optional qlxgbe pci
dev/qlxgbe/ql_isr.c optional qlxgbe pci
dev/qlxgbe/ql_misc.c optional qlxgbe pci
dev/qlxgbe/ql_os.c optional qlxgbe pci
dev/qlxgbe/ql_reset.c optional qlxgbe pci
dev/sfxge/common/efx_bootcfg.c optional sfxge inet pci
dev/sfxge/common/efx_ev.c optional sfxge inet pci
dev/sfxge/common/efx_filter.c optional sfxge inet pci

102
sys/dev/qlxgbe/README.txt Normal file
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@ -0,0 +1,102 @@
# $FreeBSD$
README File
QLogic 8300 series Dual Port
10 Gigabit Ethernet & CNA Adapter Driver for FreeBSD 9.x/10.x
QLogic Corporation.
All rights reserved.
Table of Contents
1. Package Contents
2. OS Support
3. Supported Features
4. Using the Driver
4.1 Installing the driver
4.2 Removing the driver
5. Driver Parameters
6. Additional Notes
7. Contacting Support
1. Package Contents
* Documentation
- README (this document) version:1.0
- Release Notes Version:1.0
* Driver (if_qlxgbe.ko)
- FreeBSD 9.x/10.x
* Firmware: pre-flashed on QLogic adapter;
2. OS Support
The Qlogic 83xx 10Gigabit Ethernet/CNA driver is compatible with the
following OS platforms:
* FreeBSD 9.x/10.x (64-bit) [Intel EM64T, AMD64]
3. Supported Features
10Gigabit Ethernet NIC/CNA driver supports following features
* Large Segment Offload over TCP IPV4
* Large Segment Offload over TCP IPV6
* Receive Side scaling
* TCP over IPv4 checksum offload
* UDP over IPv4 checksum offload
* IPV4 checksum offload
* TCP over IPv6 checksum offload
* UDP over IPv6 checksum offload
* Jumbo frames
* VLAN Tag
4. Using the driver
4.1 Installing the driver
- copy the driver file (if_qlxgbe.ko) into some directory (say qla_driver)
- cd <to qla_driver>
- kldload -v ./if_qlxgbe.ko
4.2 Removing the driver
- kldunload if_qlxgbe
5. Parameters to set prior to installing the driver
- Add the following lines to /etc/sysctl.conf and reboot the machine prior
to installing the driver
kern.ipc.nmbjumbo9=262144
net.inet.tcp.recvbuf_max=262144
net.inet.tcp.recvbuf_inc=16384
kern.ipc.nmbclusters=1000000
kern.ipc.maxsockbuf=2097152
net.inet.tcp.recvspace=131072
net.inet.tcp.sendbuf_max=262144
net.inet.tcp.sendspace=65536
- If you do not want to reboot the system please run the following commands
login or su to root
sysctl kern.ipc.nmbjumbo9=262144
sysctl net.inet.tcp.recvbuf_max=262144
sysctl net.inet.tcp.recvbuf_inc=16384
sysctl kern.ipc.nmbclusters=1000000
sysctl kern.ipc.maxsockbuf=2097152
sysctl net.inet.tcp.recvspace=131072
sysctl net.inet.tcp.sendbuf_max=262144
sysctl net.inet.tcp.sendspace=65536
6. Compile options Makefile if building driver from sources
None
7. Contacting Support
Please feel free to contact your QLogic approved reseller or QLogic
Technical Support at any phase of integration for assistance. QLogic
Technical Support can be reached by the following methods:
Web: http://support.qlogic.com
E-mail: support@qlogic.com
(c) Copyright 2013-14. All rights reserved worldwide. QLogic, the QLogic
logo, and the Powered by QLogic logo are registered trademarks of
QLogic Corporation. All other brand and product names are trademarks
or registered trademarks of their respective owners.

260
sys/dev/qlxgbe/ql_dbg.c Normal file
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@ -0,0 +1,260 @@
/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* File : ql_dbg.c
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "ql_os.h"
#include "ql_hw.h"
#include "ql_def.h"
#include "ql_inline.h"
#include "ql_ver.h"
#include "ql_glbl.h"
#include "ql_dbg.h"
/*
* Name: ql_dump_buf32
* Function: dumps a buffer as 32 bit words
*/
void ql_dump_buf32(qla_host_t *ha, const char *msg, void *dbuf32, uint32_t len32)
{
device_t dev;
uint32_t i = 0;
uint32_t *buf;
dev = ha->pci_dev;
buf = dbuf32;
device_printf(dev, "%s: %s dump start\n", __func__, msg);
while (len32 >= 4) {
device_printf(dev,"0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
i, buf[0], buf[1], buf[2], buf[3]);
i += 4 * 4;
len32 -= 4;
buf += 4;
}
switch (len32) {
case 1:
device_printf(dev,"0x%08x: 0x%08x\n", i, buf[0]);
break;
case 2:
device_printf(dev,"0x%08x: 0x%08x 0x%08x\n", i, buf[0], buf[1]);
break;
case 3:
device_printf(dev,"0x%08x: 0x%08x 0x%08x 0x%08x\n",
i, buf[0], buf[1], buf[2]);
break;
default:
break;
}
device_printf(dev, "%s: %s dump end\n", __func__, msg);
}
/*
* Name: ql_dump_buf16
* Function: dumps a buffer as 16 bit words
*/
void ql_dump_buf16(qla_host_t *ha, const char *msg, void *dbuf16, uint32_t len16)
{
device_t dev;
uint32_t i = 0;
uint16_t *buf;
dev = ha->pci_dev;
buf = dbuf16;
device_printf(dev, "%s: %s dump start\n", __func__, msg);
while (len16 >= 8) {
device_printf(dev,"0x%08x: 0x%04x 0x%04x 0x%04x 0x%04x"
" 0x%04x 0x%04x 0x%04x 0x%04x\n", i, buf[0],
buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
i += 16;
len16 -= 8;
buf += 8;
}
switch (len16) {
case 1:
device_printf(dev,"0x%08x: 0x%04x\n", i, buf[0]);
break;
case 2:
device_printf(dev,"0x%08x: 0x%04x 0x%04x\n", i, buf[0], buf[1]);
break;
case 3:
device_printf(dev,"0x%08x: 0x%04x 0x%04x 0x%04x\n",
i, buf[0], buf[1], buf[2]);
break;
case 4:
device_printf(dev,"0x%08x: 0x%04x 0x%04x 0x%04x 0x%04x\n", i,
buf[0], buf[1], buf[2], buf[3]);
break;
case 5:
device_printf(dev,"0x%08x:"
" 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4]);
break;
case 6:
device_printf(dev,"0x%08x:"
" 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
break;
case 7:
device_printf(dev,"0x%04x: 0x%04x 0x%04x 0x%04x 0x%04x"
" 0x%04x 0x%04x 0x%04x\n", i, buf[0], buf[1],
buf[2], buf[3], buf[4], buf[5], buf[6]);
break;
default:
break;
}
device_printf(dev, "%s: %s dump end\n", __func__, msg);
}
/*
* Name: ql_dump_buf8
* Function: dumps a buffer as bytes
*/
void ql_dump_buf8(qla_host_t *ha, const char *msg, void *dbuf, uint32_t len)
{
device_t dev;
uint32_t i = 0;
uint8_t *buf;
dev = ha->pci_dev;
buf = dbuf;
device_printf(dev, "%s: %s 0x%x dump start\n", __func__, msg, len);
while (len >= 16) {
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3],
buf[4], buf[5], buf[6], buf[7],
buf[8], buf[9], buf[10], buf[11],
buf[12], buf[13], buf[14], buf[15]);
i += 16;
len -= 16;
buf += 16;
}
switch (len) {
case 1:
device_printf(dev,"0x%08x: %02x\n", i, buf[0]);
break;
case 2:
device_printf(dev,"0x%08x: %02x %02x\n", i, buf[0], buf[1]);
break;
case 3:
device_printf(dev,"0x%08x: %02x %02x %02x\n",
i, buf[0], buf[1], buf[2]);
break;
case 4:
device_printf(dev,"0x%08x: %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3]);
break;
case 5:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4]);
break;
case 6:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
break;
case 7:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]);
break;
case 8:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7]);
break;
case 9:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8]);
break;
case 10:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9]);
break;
case 11:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9], buf[10]);
break;
case 12:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9], buf[10], buf[11]);
break;
case 13:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9], buf[10], buf[11], buf[12]);
break;
case 14:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
buf[13]);
break;
case 15:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
buf[13], buf[14]);
break;
default:
break;
}
device_printf(dev, "%s: %s dump end\n", __func__, msg);
}

98
sys/dev/qlxgbe/ql_dbg.h Normal file
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@ -0,0 +1,98 @@
/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File : ql_dbg.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QL_DBG_H_
#define _QL_DBG_H_
extern void ql_dump_buf8(qla_host_t *ha, const char *str, void *dbuf,
uint32_t len);
extern void ql_dump_buf16(qla_host_t *ha, const char *str, void *dbuf,
uint32_t len16);
extern void ql_dump_buf32(qla_host_t *ha, const char *str, void *dbuf,
uint32_t len32);
#define INJCT_RX_RXB_INVAL 0x00001
#define INJCT_RX_MP_NULL 0x00002
#define INJCT_LRO_RXB_INVAL 0x00003
#define INJCT_LRO_MP_NULL 0x00004
#define INJCT_NUM_HNDLE_INVALID 0x00005
#define INJCT_RDWR_INDREG_FAILURE 0x00006
#define INJCT_RDWR_OFFCHIPMEM_FAILURE 0x00007
#define INJCT_MBX_CMD_FAILURE 0x00008
#define INJCT_HEARTBEAT_FAILURE 0x00009
#define INJCT_TEMPERATURE_FAILURE 0x0000A
#ifdef QL_DBG
#define QL_DPRINT1(ha, x) if (ha->dbg_level & 0x0001) device_printf x
#define QL_DPRINT2(ha, x) if (ha->dbg_level & 0x0002) device_printf x
#define QL_DPRINT4(ha, x) if (ha->dbg_level & 0x0004) device_printf x
#define QL_DPRINT8(ha, x) if (ha->dbg_level & 0x0008) device_printf x
#define QL_DPRINT10(ha, x) if (ha->dbg_level & 0x0010) device_printf x
#define QL_DPRINT20(ha, x) if (ha->dbg_level & 0x0020) device_printf x
#define QL_DPRINT40(ha, x) if (ha->dbg_level & 0x0040) device_printf x
#define QL_DPRINT80(ha, x) if (ha->dbg_level & 0x0080) device_printf x
#define QL_DUMP_BUFFER8(h, s, b, n) if (h->dbg_level & 0x08000000)\
qla_dump_buf8(h, s, b, n)
#define QL_DUMP_BUFFER16(h, s, b, n) if (h->dbg_level & 0x08000000)\
qla_dump_buf16(h, s, b, n)
#define QL_DUMP_BUFFER32(h, s, b, n) if (h->dbg_level & 0x08000000)\
qla_dump_buf32(h, s, b, n)
#define QL_ASSERT(ha, x, y) if (!x && !ha->err_inject) panic y
#define QL_ERR_INJECT(ha, val) (ha->err_inject == val)
#else
#define QL_DPRINT1(ha, x)
#define QL_DPRINT2(ha, x)
#define QL_DPRINT4(ha, x)
#define QL_DPRINT8(ha, x)
#define QL_DPRINT10(ha, x)
#define QL_DPRINT20(ha, x)
#define QL_DPRINT40(ha, x)
#define QL_DPRINT80(ha, x)
#define QL_DUMP_BUFFER8(h, s, b, n)
#define QL_DUMP_BUFFER16(h, s, b, n)
#define QL_DUMP_BUFFER32(h, s, b, n)
#define QL_ASSERT(ha, x, y)
#define QL_ERR_INJECT(ha, val) 0
#endif
#endif /* #ifndef _QL_DBG_H_ */

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sys/dev/qlxgbe/ql_def.h Normal file
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@ -0,0 +1,258 @@
/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: ql_def.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QL_DEF_H_
#define _QL_DEF_H_
#define BIT_0 (0x1 << 0)
#define BIT_1 (0x1 << 1)
#define BIT_2 (0x1 << 2)
#define BIT_3 (0x1 << 3)
#define BIT_4 (0x1 << 4)
#define BIT_5 (0x1 << 5)
#define BIT_6 (0x1 << 6)
#define BIT_7 (0x1 << 7)
#define BIT_8 (0x1 << 8)
#define BIT_9 (0x1 << 9)
#define BIT_10 (0x1 << 10)
#define BIT_11 (0x1 << 11)
#define BIT_12 (0x1 << 12)
#define BIT_13 (0x1 << 13)
#define BIT_14 (0x1 << 14)
#define BIT_15 (0x1 << 15)
#define BIT_16 (0x1 << 16)
#define BIT_17 (0x1 << 17)
#define BIT_18 (0x1 << 18)
#define BIT_19 (0x1 << 19)
#define BIT_20 (0x1 << 20)
#define BIT_21 (0x1 << 21)
#define BIT_22 (0x1 << 22)
#define BIT_23 (0x1 << 23)
#define BIT_24 (0x1 << 24)
#define BIT_25 (0x1 << 25)
#define BIT_26 (0x1 << 26)
#define BIT_27 (0x1 << 27)
#define BIT_28 (0x1 << 28)
#define BIT_29 (0x1 << 29)
#define BIT_30 (0x1 << 30)
#define BIT_31 (0x1 << 31)
struct qla_rx_buf {
struct mbuf *m_head;
bus_dmamap_t map;
bus_addr_t paddr;
uint32_t handle;
void *next;
};
typedef struct qla_rx_buf qla_rx_buf_t;
struct qla_rx_ring {
qla_rx_buf_t rx_buf[NUM_RX_DESCRIPTORS];
};
typedef struct qla_rx_ring qla_rx_ring_t;
struct qla_tx_buf {
struct mbuf *m_head;
bus_dmamap_t map;
};
typedef struct qla_tx_buf qla_tx_buf_t;
#define QLA_MAX_SEGMENTS 62 /* maximum # of segs in a sg list */
#define QLA_MAX_MTU 9000
#define QLA_STD_FRAME_SIZE 1514
#define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22)
/* Number of MSIX/MSI Vectors required */
struct qla_ivec {
uint32_t sds_idx;
void *ha;
struct resource *irq;
void *handle;
int irq_rid;
};
typedef struct qla_ivec qla_ivec_t;
#define QLA_WATCHDOG_CALLOUT_TICKS 1
typedef struct _qla_tx_ring {
qla_tx_buf_t tx_buf[NUM_TX_DESCRIPTORS];
uint64_t count;
} qla_tx_ring_t;
/*
* Adapter structure contains the hardware independant information of the
* pci function.
*/
struct qla_host {
volatile struct {
volatile uint32_t
qla_callout_init :1,
qla_watchdog_active :1,
qla_watchdog_exit :1,
qla_watchdog_pause :1,
lro_init :1,
stop_rcv :1,
parent_tag :1,
lock_init :1;
} flags;
volatile uint32_t qla_watchdog_exited;
volatile uint32_t qla_watchdog_paused;
volatile uint32_t qla_initiate_recovery;
device_t pci_dev;
uint16_t watchdog_ticks;
uint8_t pci_func;
uint8_t resvd;
/* ioctl related */
struct cdev *ioctl_dev;
/* register mapping */
struct resource *pci_reg;
int reg_rid;
struct resource *pci_reg1;
int reg_rid1;
/* interrupts */
struct resource *mbx_irq;
void *mbx_handle;
int mbx_irq_rid;
int msix_count;
qla_ivec_t irq_vec[MAX_SDS_RINGS];
/* parent dma tag */
bus_dma_tag_t parent_tag;
/* interface to o.s */
struct ifnet *ifp;
struct ifmedia media;
uint16_t max_frame_size;
uint16_t rsrvd0;
int if_flags;
/* hardware access lock */
struct mtx hw_lock;
volatile uint32_t hw_lock_held;
/* transmit and receive buffers */
uint32_t txr_idx; /* index of the current tx ring */
qla_tx_ring_t tx_ring[NUM_TX_RINGS];
bus_dma_tag_t tx_tag;
struct task tx_task;
struct taskqueue *tx_tq;
struct callout tx_callout;
struct mtx tx_lock;
qla_rx_ring_t rx_ring[MAX_RDS_RINGS];
bus_dma_tag_t rx_tag;
uint32_t std_replenish;
qla_rx_buf_t *rxb_free;
uint32_t rxb_free_count;
volatile uint32_t posting;
/* stats */
uint32_t err_m_getcl;
uint32_t err_m_getjcl;
uint32_t err_tx_dmamap_create;
uint32_t err_tx_dmamap_load;
uint32_t err_tx_defrag;
uint64_t rx_frames;
uint64_t rx_bytes;
uint64_t lro_pkt_count;
uint64_t lro_bytes;
uint64_t ipv4_lro;
uint64_t ipv6_lro;
uint64_t tx_frames;
uint64_t tx_bytes;
uint64_t tx_tso_frames;
uint64_t hw_vlan_tx_frames;
uint32_t fw_ver_major;
uint32_t fw_ver_minor;
uint32_t fw_ver_sub;
uint32_t fw_ver_build;
/* hardware specific */
qla_hw_t hw;
/* debug stuff */
volatile const char *qla_lock;
volatile const char *qla_unlock;
uint32_t dbg_level;
uint8_t fw_ver_str[32];
/* Error Injection Related */
uint32_t err_inject;
struct task err_task;
struct taskqueue *err_tq;
/* Peer Device */
device_t peer_dev;
volatile uint32_t msg_from_peer;
#define QL_PEER_MSG_RESET 0x01
#define QL_PEER_MSG_ACK 0x02
};
typedef struct qla_host qla_host_t;
/* note that align has to be a power of 2 */
#define QL_ALIGN(size, align) (size + (align - 1)) & ~(align - 1);
#define QL_MIN(x, y) ((x < y) ? x : y)
#define QL_RUNNING(ifp) \
((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \
IFF_DRV_RUNNING)
/* Return 0, if identical, else 1 */
#define QL_MAC_CMP(mac1, mac2) \
((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
(*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
#endif /* #ifndef _QL_DEF_H_ */

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: ql_glbl.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
* Content: Contains prototypes of the exported functions from each file.
*/
#ifndef _QL_GLBL_H_
#define _QL_GLBL_H_
/*
* from ql_isr.c
*/
extern void ql_mbx_isr(void *arg);
extern void ql_isr(void *arg);
/*
* from ql_os.c
*/
extern int ql_alloc_dmabuf(qla_host_t *ha, qla_dma_t *dma_buf);
extern void ql_free_dmabuf(qla_host_t *ha, qla_dma_t *dma_buf);
extern int ql_get_mbuf(qla_host_t *ha, qla_rx_buf_t *rxb, struct mbuf *nmp);
/*
* from ql_hw.c
*/
extern int ql_alloc_dma(qla_host_t *ha);
extern void ql_free_dma(qla_host_t *ha);
extern void ql_hw_add_sysctls(qla_host_t *ha);
extern int ql_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
uint32_t tx_idx, struct mbuf *mp, uint32_t txr_idx);
extern int ql_init_hw_if(qla_host_t *ha);
extern int ql_hw_set_multi(qla_host_t *ha, uint8_t *mta, uint32_t mcnt,
uint32_t add_multi);
extern void ql_del_hw_if(qla_host_t *ha);
extern int ql_set_promisc(qla_host_t *ha);
extern int ql_set_allmulti(qla_host_t *ha);
extern void ql_update_link_state(qla_host_t *ha);
extern void ql_hw_tx_done(qla_host_t *ha);
extern int ql_set_max_mtu(qla_host_t *ha, uint32_t mtu, uint16_t cntxt_id);
extern void ql_hw_stop_rcv(qla_host_t *ha);
extern void ql_get_stats(qla_host_t *ha);
extern void ql_hw_link_status(qla_host_t *ha);
extern int ql_hw_check_health(qla_host_t *ha);
extern void ql_minidump(qla_host_t *ha);
/*
* from ql_misc.c
*/
extern int ql_init_hw(qla_host_t *ha);
extern int ql_rdwr_indreg32(qla_host_t *ha, uint32_t addr, uint32_t *val,
uint32_t rd);
extern int ql_rd_flash32(qla_host_t *ha, uint32_t addr, uint32_t *data);
extern int ql_rdwr_offchip_mem(qla_host_t *ha, uint64_t addr,
q80_offchip_mem_val_t *val, uint32_t rd);
extern void ql_read_mac_addr(qla_host_t *ha);
extern int ql_erase_flash(qla_host_t *ha, uint32_t off, uint32_t size);
extern int ql_wr_flash_buffer(qla_host_t *ha, uint32_t off, uint32_t size,
void *buf);
extern int ql_stop_sequence(qla_host_t *ha);
extern int ql_start_sequence(qla_host_t *ha, uint16_t index);
/*
* from ql_ioctl.c
*/
extern int ql_make_cdev(qla_host_t *ha);
extern void ql_del_cdev(qla_host_t *ha);
#endif /* #ifndef_QL_GLBL_H_ */

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: ql_inline.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QL_INLINE_H_
#define _QL_INLINE_H_
#define QL8_SEMLOCK_TIMEOUT 1000/* QLA8020 Semaphore Lock Timeout 10ms */
/*
* Inline functions for hardware semaphores
*/
/*
* Name: qla_sem_lock
* Function: Locks one of the semaphore registers (semaphore 2,3,5 & 7)
* If the id_reg is valid, then id_val is written into it.
* This is for debugging purpose
* Returns: 0 on success; otherwise its failed.
*/
static __inline int
qla_sem_lock(qla_host_t *ha, uint32_t sem_reg, uint32_t id_reg, uint32_t id_val)
{
int count = QL8_SEMLOCK_TIMEOUT;
while (count) {
if ((READ_REG32(ha, sem_reg) & BIT_0))
break;
count--;
if (!count)
return(-1);
qla_mdelay(__func__, 10);
}
if (id_reg)
WRITE_REG32(ha, id_reg, id_val);
return(0);
}
/*
* Name: qla_sem_unlock
* Function: Unlocks the semaphore registers (semaphore 2,3,5 & 7)
* previously locked by qla_sem_lock()
*/
static __inline void
qla_sem_unlock(qla_host_t *ha, uint32_t sem_reg)
{
READ_REG32(ha, sem_reg);
}
static __inline int
qla_get_ifq_snd_maxlen(qla_host_t *ha)
{
return(((NUM_TX_DESCRIPTORS * 4) - 1));
}
static __inline uint32_t
qla_get_optics(qla_host_t *ha)
{
uint32_t link_speed;
link_speed = READ_REG32(ha, Q8_LINK_SPEED_0);
if (ha->pci_func == 0)
link_speed = link_speed & 0xFF;
else
link_speed = (link_speed >> 8) & 0xFF;
switch (link_speed) {
case 0x1:
link_speed = IFM_100_FX;
break;
case 0x10:
link_speed = IFM_1000_SX;
break;
default:
if ((ha->hw.module_type == 0x4) ||
(ha->hw.module_type == 0x5) ||
(ha->hw.module_type == 0x6))
link_speed = (IFM_10G_TWINAX);
else
link_speed = (IFM_10G_LR | IFM_10G_SR);
break;
}
return(link_speed);
}
static __inline uint8_t *
qla_get_mac_addr(qla_host_t *ha)
{
return (ha->hw.mac_addr);
}
static __inline void
qla_set_hw_rcv_desc(qla_host_t *ha, uint32_t r_idx, uint32_t index,
uint32_t handle, bus_addr_t paddr, uint32_t buf_size)
{
volatile q80_recv_desc_t *rcv_desc;
rcv_desc = (q80_recv_desc_t *)ha->hw.dma_buf.rds_ring[r_idx].dma_b;
rcv_desc += index;
rcv_desc->handle = (uint16_t)handle;
rcv_desc->buf_size = buf_size;
rcv_desc->buf_addr = paddr;
return;
}
static __inline void
qla_init_hw_rcv_descriptors(qla_host_t *ha)
{
int i;
for (i = 0; i < ha->hw.num_rds_rings; i++)
bzero((void *)ha->hw.dma_buf.rds_ring[i].dma_b,
(sizeof(q80_recv_desc_t) * NUM_RX_DESCRIPTORS));
}
static __inline int
qla_lock(qla_host_t *ha, const char *str, uint32_t no_delay)
{
int ret = -1;
while (1) {
mtx_lock(&ha->hw_lock);
if (!ha->hw_lock_held) {
ha->hw_lock_held = 1;
ha->qla_lock = str;
ret = 0;
mtx_unlock(&ha->hw_lock);
break;
}
mtx_unlock(&ha->hw_lock);
if (no_delay)
break;
else
qla_mdelay(__func__, 1);
}
return (ret);
}
static __inline void
qla_unlock(qla_host_t *ha, const char *str)
{
mtx_lock(&ha->hw_lock);
ha->hw_lock_held = 0;
ha->qla_unlock = str;
mtx_unlock(&ha->hw_lock);
}
#endif /* #ifndef _QL_INLINE_H_ */

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* File: ql_ioctl.c
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "ql_os.h"
#include "ql_hw.h"
#include "ql_def.h"
#include "ql_inline.h"
#include "ql_glbl.h"
#include "ql_ioctl.h"
static int ql_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
struct thread *td);
static struct cdevsw qla_cdevsw = {
.d_version = D_VERSION,
.d_ioctl = ql_eioctl,
.d_name = "qlcnic",
};
int
ql_make_cdev(qla_host_t *ha)
{
ha->ioctl_dev = make_dev(&qla_cdevsw,
ha->ifp->if_dunit,
UID_ROOT,
GID_WHEEL,
0600,
"%s",
if_name(ha->ifp));
if (ha->ioctl_dev == NULL)
return (-1);
ha->ioctl_dev->si_drv1 = ha;
return (0);
}
void
ql_del_cdev(qla_host_t *ha)
{
if (ha->ioctl_dev != NULL)
destroy_dev(ha->ioctl_dev);
return;
}
static int
ql_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
struct thread *td)
{
qla_host_t *ha;
int rval = 0;
device_t pci_dev;
struct ifnet *ifp;
q80_offchip_mem_val_t val;
qla_rd_pci_ids_t *pci_ids;
qla_rd_fw_dump_t *fw_dump;
union {
qla_reg_val_t *rv;
qla_rd_flash_t *rdf;
qla_wr_flash_t *wrf;
qla_erase_flash_t *erf;
qla_offchip_mem_val_t *mem;
} u;
if ((ha = (qla_host_t *)dev->si_drv1) == NULL)
return ENXIO;
pci_dev= ha->pci_dev;
switch(cmd) {
case QLA_RDWR_REG:
u.rv = (qla_reg_val_t *)data;
if (u.rv->direct) {
if (u.rv->rd) {
u.rv->val = READ_REG32(ha, u.rv->reg);
} else {
WRITE_REG32(ha, u.rv->reg, u.rv->val);
}
} else {
if ((rval = ql_rdwr_indreg32(ha, u.rv->reg, &u.rv->val,
u.rv->rd)))
rval = ENXIO;
}
break;
case QLA_RD_FLASH:
if (!ha->hw.flags.fdt_valid) {
rval = EIO;
break;
}
u.rdf = (qla_rd_flash_t *)data;
if ((rval = ql_rd_flash32(ha, u.rdf->off, &u.rdf->data)))
rval = ENXIO;
break;
case QLA_WR_FLASH:
ifp = ha->ifp;
if (ifp == NULL) {
rval = ENXIO;
break;
}
if (ifp->if_drv_flags & (IFF_DRV_OACTIVE | IFF_DRV_RUNNING)) {
rval = ENXIO;
break;
}
if (!ha->hw.flags.fdt_valid) {
rval = EIO;
break;
}
u.wrf = (qla_wr_flash_t *)data;
if ((rval = ql_wr_flash_buffer(ha, u.wrf->off, u.wrf->size,
u.wrf->buffer))) {
printf("flash write failed[%d]\n", rval);
rval = ENXIO;
}
break;
case QLA_ERASE_FLASH:
ifp = ha->ifp;
if (ifp == NULL) {
rval = ENXIO;
break;
}
if (ifp->if_drv_flags & (IFF_DRV_OACTIVE | IFF_DRV_RUNNING)) {
rval = ENXIO;
break;
}
if (!ha->hw.flags.fdt_valid) {
rval = EIO;
break;
}
u.erf = (qla_erase_flash_t *)data;
if ((rval = ql_erase_flash(ha, u.erf->off,
u.erf->size))) {
printf("flash erase failed[%d]\n", rval);
rval = ENXIO;
}
break;
case QLA_RDWR_MS_MEM:
u.mem = (qla_offchip_mem_val_t *)data;
if ((rval = ql_rdwr_offchip_mem(ha, u.mem->off, &val,
u.mem->rd)))
rval = ENXIO;
else {
u.mem->data_lo = val.data_lo;
u.mem->data_hi = val.data_hi;
u.mem->data_ulo = val.data_ulo;
u.mem->data_uhi = val.data_uhi;
}
break;
case QLA_RD_FW_DUMP_SIZE:
if (ha->hw.mdump_init == 0) {
rval = EINVAL;
break;
}
fw_dump = (qla_rd_fw_dump_t *)data;
fw_dump->template_size = ha->hw.dma_buf.minidump.size;
fw_dump->pci_func = ha->pci_func;
break;
case QLA_RD_FW_DUMP:
if (ha->hw.mdump_init == 0) {
rval = EINVAL;
break;
}
fw_dump = (qla_rd_fw_dump_t *)data;
if ((rval = copyout(ha->hw.dma_buf.minidump.dma_b,
fw_dump->md_template, fw_dump->template_size)))
rval = ENXIO;
break;
case QLA_RD_PCI_IDS:
pci_ids = (qla_rd_pci_ids_t *)data;
pci_ids->ven_id = pci_get_vendor(pci_dev);
pci_ids->dev_id = pci_get_device(pci_dev);
pci_ids->subsys_ven_id = pci_get_subvendor(pci_dev);
pci_ids->subsys_dev_id = pci_get_subdevice(pci_dev);
pci_ids->rev_id = pci_read_config(pci_dev, PCIR_REVID, 1);
break;
default:
break;
}
return rval;
}

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: ql_ioctl.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QL_IOCTL_H_
#define _QL_IOCTL_H_
#include <sys/ioccom.h>
struct qla_reg_val {
uint16_t rd;
uint16_t direct;
uint32_t reg;
uint32_t val;
};
typedef struct qla_reg_val qla_reg_val_t;
struct qla_rd_flash {
uint32_t off;
uint32_t data;
};
typedef struct qla_rd_flash qla_rd_flash_t;
struct qla_wr_flash {
uint32_t off;
uint32_t size;
void *buffer;
uint32_t pattern;
};
typedef struct qla_wr_flash qla_wr_flash_t;
struct qla_erase_flash {
uint32_t off;
uint32_t size;
};
typedef struct qla_erase_flash qla_erase_flash_t;
struct qla_rd_pci_ids {
uint16_t ven_id;
uint16_t dev_id;
uint16_t subsys_ven_id;
uint16_t subsys_dev_id;
uint8_t rev_id;
};
typedef struct qla_rd_pci_ids qla_rd_pci_ids_t;
/*
* structure encapsulating the value to read/write from/to offchip (MS) memory
*/
struct qla_offchip_mem_val {
uint16_t rd;
uint64_t off;
uint32_t data_lo;
uint32_t data_hi;
uint32_t data_ulo;
uint32_t data_uhi;
};
typedef struct qla_offchip_mem_val qla_offchip_mem_val_t;
struct qla_rd_fw_dump {
uint16_t pci_func;
uint32_t template_size;
void *md_template;
};
typedef struct qla_rd_fw_dump qla_rd_fw_dump_t;
/*
* Read/Write Register
*/
#define QLA_RDWR_REG _IOWR('q', 1, qla_reg_val_t)
/*
* Read Flash
*/
#define QLA_RD_FLASH _IOWR('q', 2, qla_rd_flash_t)
/*
* Write Flash
*/
#define QLA_WR_FLASH _IOWR('q', 3, qla_wr_flash_t)
/*
* Read Offchip (MS) Memory
*/
#define QLA_RDWR_MS_MEM _IOWR('q', 4, qla_offchip_mem_val_t)
/*
* Erase Flash
*/
#define QLA_ERASE_FLASH _IOWR('q', 5, qla_erase_flash_t)
/*
* Read PCI IDs
*/
#define QLA_RD_PCI_IDS _IOWR('q', 6, qla_rd_pci_ids_t)
/*
* Read Minidump Template Size
*/
#define QLA_RD_FW_DUMP_SIZE _IOWR('q', 7, qla_rd_fw_dump_t)
/*
* Read Minidump Template
*/
#define QLA_RD_FW_DUMP _IOWR('q', 8, qla_rd_fw_dump_t)
#endif /* #ifndef _QL_IOCTL_H_ */

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* File: ql_isr.c
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "ql_os.h"
#include "ql_hw.h"
#include "ql_def.h"
#include "ql_inline.h"
#include "ql_ver.h"
#include "ql_glbl.h"
#include "ql_dbg.h"
static void qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp,
uint32_t r_idx);
static void
qla_rcv_error(qla_host_t *ha)
{
ha->flags.stop_rcv = 1;
ha->qla_initiate_recovery = 1;
}
/*
* Name: qla_rx_intr
* Function: Handles normal ethernet frames received
*/
static void
qla_rx_intr(qla_host_t *ha, qla_sgl_rcv_t *sgc, uint32_t sds_idx)
{
qla_rx_buf_t *rxb;
struct mbuf *mp = NULL, *mpf = NULL, *mpl = NULL;
struct ifnet *ifp = ha->ifp;
qla_sds_t *sdsp;
struct ether_vlan_header *eh;
uint32_t i, rem_len = 0;
uint32_t r_idx = 0;
qla_rx_ring_t *rx_ring;
if (ha->hw.num_rds_rings > 1)
r_idx = sds_idx;
ha->hw.rds[r_idx].count++;
sdsp = &ha->hw.sds[sds_idx];
rx_ring = &ha->rx_ring[r_idx];
for (i = 0; i < sgc->num_handles; i++) {
rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF];
QL_ASSERT(ha, (rxb != NULL),
("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\
sds_idx));
if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_RX_RXB_INVAL)) {
/* log the error */
device_printf(ha->pci_dev,
"%s invalid rxb[%d, %d, 0x%04x]\n",
__func__, sds_idx, i, sgc->handle[i]);
qla_rcv_error(ha);
return;
}
mp = rxb->m_head;
if (i == 0)
mpf = mp;
QL_ASSERT(ha, (mp != NULL),
("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\
sds_idx));
bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
rxb->m_head = NULL;
rxb->next = sdsp->rxb_free;
sdsp->rxb_free = rxb;
sdsp->rx_free++;
if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_RX_MP_NULL)) {
/* log the error */
device_printf(ha->pci_dev,
"%s mp == NULL [%d, %d, 0x%04x]\n",
__func__, sds_idx, i, sgc->handle[i]);
qla_rcv_error(ha);
return;
}
if (i == 0) {
mpl = mpf = mp;
mp->m_flags |= M_PKTHDR;
mp->m_pkthdr.len = sgc->pkt_length;
mp->m_pkthdr.rcvif = ifp;
rem_len = mp->m_pkthdr.len;
} else {
mp->m_flags &= ~M_PKTHDR;
mpl->m_next = mp;
mpl = mp;
rem_len = rem_len - mp->m_len;
}
}
mpl->m_len = rem_len;
eh = mtod(mpf, struct ether_vlan_header *);
if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
uint32_t *data = (uint32_t *)eh;
mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
mpf->m_flags |= M_VLANTAG;
*(data + 3) = *(data + 2);
*(data + 2) = *(data + 1);
*(data + 1) = *data;
m_adj(mpf, ETHER_VLAN_ENCAP_LEN);
}
if (sgc->chksum_status == Q8_STAT_DESC_STATUS_CHKSUM_OK) {
mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID |
CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
mpf->m_pkthdr.csum_data = 0xFFFF;
} else {
mpf->m_pkthdr.csum_flags = 0;
}
ifp->if_ipackets++;
mpf->m_pkthdr.flowid = sgc->rss_hash;
mpf->m_flags |= M_FLOWID;
(*ifp->if_input)(ifp, mpf);
if (sdsp->rx_free > ha->std_replenish)
qla_replenish_normal_rx(ha, sdsp, r_idx);
return;
}
#define QLA_TCP_HDR_SIZE 20
#define QLA_TCP_TS_OPTION_SIZE 12
/*
* Name: qla_lro_intr
* Function: Handles normal ethernet frames received
*/
static int
qla_lro_intr(qla_host_t *ha, qla_sgl_lro_t *sgc, uint32_t sds_idx)
{
qla_rx_buf_t *rxb;
struct mbuf *mp = NULL, *mpf = NULL, *mpl = NULL;
struct ifnet *ifp = ha->ifp;
qla_sds_t *sdsp;
struct ether_vlan_header *eh;
uint32_t i, rem_len = 0, pkt_length, iplen;
struct tcphdr *th;
struct ip *ip = NULL;
struct ip6_hdr *ip6 = NULL;
uint16_t etype;
uint32_t r_idx = 0;
qla_rx_ring_t *rx_ring;
if (ha->hw.num_rds_rings > 1)
r_idx = sds_idx;
ha->hw.rds[r_idx].count++;
rx_ring = &ha->rx_ring[r_idx];
ha->lro_pkt_count++;
sdsp = &ha->hw.sds[sds_idx];
pkt_length = sgc->payload_length + sgc->l4_offset;
if (sgc->flags & Q8_LRO_COMP_TS) {
pkt_length += QLA_TCP_HDR_SIZE + QLA_TCP_TS_OPTION_SIZE;
} else {
pkt_length += QLA_TCP_HDR_SIZE;
}
ha->lro_bytes += pkt_length;
for (i = 0; i < sgc->num_handles; i++) {
rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF];
QL_ASSERT(ha, (rxb != NULL),
("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\
sds_idx));
if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_RXB_INVAL)) {
/* log the error */
device_printf(ha->pci_dev,
"%s invalid rxb[%d, %d, 0x%04x]\n",
__func__, sds_idx, i, sgc->handle[i]);
qla_rcv_error(ha);
return (0);
}
mp = rxb->m_head;
if (i == 0)
mpf = mp;
QL_ASSERT(ha, (mp != NULL),
("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\
sds_idx));
bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
rxb->m_head = NULL;
rxb->next = sdsp->rxb_free;
sdsp->rxb_free = rxb;
sdsp->rx_free++;
if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_MP_NULL)) {
/* log the error */
device_printf(ha->pci_dev,
"%s mp == NULL [%d, %d, 0x%04x]\n",
__func__, sds_idx, i, sgc->handle[i]);
qla_rcv_error(ha);
return (0);
}
if (i == 0) {
mpl = mpf = mp;
mp->m_flags |= M_PKTHDR;
mp->m_pkthdr.len = pkt_length;
mp->m_pkthdr.rcvif = ifp;
rem_len = mp->m_pkthdr.len;
} else {
mp->m_flags &= ~M_PKTHDR;
mpl->m_next = mp;
mpl = mp;
rem_len = rem_len - mp->m_len;
}
}
mpl->m_len = rem_len;
th = (struct tcphdr *)(mpf->m_data + sgc->l4_offset);
if (sgc->flags & Q8_LRO_COMP_PUSH_BIT)
th->th_flags |= TH_PUSH;
m_adj(mpf, sgc->l2_offset);
eh = mtod(mpf, struct ether_vlan_header *);
if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
uint32_t *data = (uint32_t *)eh;
mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
mpf->m_flags |= M_VLANTAG;
*(data + 3) = *(data + 2);
*(data + 2) = *(data + 1);
*(data + 1) = *data;
m_adj(mpf, ETHER_VLAN_ENCAP_LEN);
etype = ntohs(eh->evl_proto);
} else {
etype = ntohs(eh->evl_encap_proto);
}
if (etype == ETHERTYPE_IP) {
ip = (struct ip *)(mpf->m_data + ETHER_HDR_LEN);
iplen = (ip->ip_hl << 2) + (th->th_off << 2) +
sgc->payload_length;
ip->ip_len = htons(iplen);
ha->ipv4_lro++;
} else if (etype == ETHERTYPE_IPV6) {
ip6 = (struct ip6_hdr *)(mpf->m_data + ETHER_HDR_LEN);
iplen = (th->th_off << 2) + sgc->payload_length;
ip6->ip6_plen = htons(iplen);
ha->ipv6_lro++;
} else {
m_freem(mpf);
if (sdsp->rx_free > ha->std_replenish)
qla_replenish_normal_rx(ha, sdsp, r_idx);
return 0;
}
mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID |
CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
mpf->m_pkthdr.csum_data = 0xFFFF;
mpf->m_pkthdr.flowid = sgc->rss_hash;
mpf->m_flags |= M_FLOWID;
ifp->if_ipackets++;
(*ifp->if_input)(ifp, mpf);
if (sdsp->rx_free > ha->std_replenish)
qla_replenish_normal_rx(ha, sdsp, r_idx);
return (0);
}
static int
qla_rcv_cont_sds(qla_host_t *ha, uint32_t sds_idx, uint32_t comp_idx,
uint32_t dcount, uint16_t *handle, uint16_t *nhandles)
{
uint32_t i;
uint16_t num_handles;
q80_stat_desc_t *sdesc;
uint32_t opcode;
*nhandles = 0;
dcount--;
for (i = 0; i < dcount; i++) {
comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
sdesc = (q80_stat_desc_t *)
&ha->hw.sds[sds_idx].sds_ring_base[comp_idx];
opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
if (!opcode) {
device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n",
__func__, (void *)sdesc->data[0],
(void *)sdesc->data[1]);
return -1;
}
num_handles = Q8_SGL_STAT_DESC_NUM_HANDLES((sdesc->data[1]));
if (!num_handles) {
device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n",
__func__, (void *)sdesc->data[0],
(void *)sdesc->data[1]);
return -1;
}
if (QL_ERR_INJECT(ha, INJCT_NUM_HNDLE_INVALID))
num_handles = -1;
switch (num_handles) {
case 1:
*handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
break;
case 2:
*handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
break;
case 3:
*handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
break;
case 4:
*handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
break;
case 5:
*handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
break;
case 6:
*handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1]));
break;
case 7:
*handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1]));
*handle++ = Q8_SGL_STAT_DESC_HANDLE7((sdesc->data[1]));
break;
default:
device_printf(ha->pci_dev,
"%s: invalid num handles %p %p\n",
__func__, (void *)sdesc->data[0],
(void *)sdesc->data[1]);
QL_ASSERT(ha, (0),\
("%s: %s [nh, sds, d0, d1]=[%d, %d, %p, %p]\n",
__func__, "invalid num handles", sds_idx, num_handles,
(void *)sdesc->data[0],(void *)sdesc->data[1]));
qla_rcv_error(ha);
return 0;
}
*nhandles = *nhandles + num_handles;
}
return 0;
}
/*
* Name: qla_rcv_isr
* Function: Main Interrupt Service Routine
*/
static uint32_t
qla_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count)
{
device_t dev;
qla_hw_t *hw;
uint32_t comp_idx, c_idx = 0, desc_count = 0, opcode;
volatile q80_stat_desc_t *sdesc, *sdesc0 = NULL;
uint32_t ret = 0;
qla_sgl_comp_t sgc;
uint16_t nhandles;
uint32_t sds_replenish_threshold = 0;
dev = ha->pci_dev;
hw = &ha->hw;
hw->sds[sds_idx].rcv_active = 1;
if (ha->flags.stop_rcv) {
hw->sds[sds_idx].rcv_active = 0;
return 0;
}
QL_DPRINT2(ha, (dev, "%s: [%d]enter\n", __func__, sds_idx));
/*
* receive interrupts
*/
comp_idx = hw->sds[sds_idx].sdsr_next;
while (count-- && !ha->flags.stop_rcv) {
sdesc = (q80_stat_desc_t *)
&hw->sds[sds_idx].sds_ring_base[comp_idx];
opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
if (!opcode)
break;
hw->sds[sds_idx].intr_count++;
switch (opcode) {
case Q8_STAT_DESC_OPCODE_RCV_PKT:
desc_count = 1;
bzero(&sgc, sizeof(qla_sgl_comp_t));
sgc.rcv.pkt_length =
Q8_STAT_DESC_TOTAL_LENGTH((sdesc->data[0]));
sgc.rcv.num_handles = 1;
sgc.rcv.handle[0] =
Q8_STAT_DESC_HANDLE((sdesc->data[0]));
sgc.rcv.chksum_status =
Q8_STAT_DESC_STATUS((sdesc->data[1]));
sgc.rcv.rss_hash =
Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
sgc.rcv.vlan_tag =
Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
}
qla_rx_intr(ha, &sgc.rcv, sds_idx);
break;
case Q8_STAT_DESC_OPCODE_SGL_RCV:
desc_count =
Q8_STAT_DESC_COUNT_SGL_RCV((sdesc->data[1]));
if (desc_count > 1) {
c_idx = (comp_idx + desc_count -1) &
(NUM_STATUS_DESCRIPTORS-1);
sdesc0 = (q80_stat_desc_t *)
&hw->sds[sds_idx].sds_ring_base[c_idx];
if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) !=
Q8_STAT_DESC_OPCODE_CONT) {
desc_count = 0;
break;
}
}
bzero(&sgc, sizeof(qla_sgl_comp_t));
sgc.rcv.pkt_length =
Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(\
(sdesc->data[0]));
sgc.rcv.chksum_status =
Q8_STAT_DESC_STATUS((sdesc->data[1]));
sgc.rcv.rss_hash =
Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
sgc.rcv.vlan_tag =
Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
}
QL_ASSERT(ha, (desc_count <= 2) ,\
("%s: [sds_idx, data0, data1]="\
"%d, %p, %p]\n", __func__, sds_idx,\
(void *)sdesc->data[0],\
(void *)sdesc->data[1]));
sgc.rcv.num_handles = 1;
sgc.rcv.handle[0] =
Q8_STAT_DESC_HANDLE((sdesc->data[0]));
if (qla_rcv_cont_sds(ha, sds_idx, comp_idx, desc_count,
&sgc.rcv.handle[1], &nhandles)) {
device_printf(dev,
"%s: [sds_idx, dcount, data0, data1]="
"[%d, %d, 0x%llx, 0x%llx]\n",
__func__, sds_idx, desc_count,
(long long unsigned int)sdesc->data[0],
(long long unsigned int)sdesc->data[1]);
desc_count = 0;
break;
}
sgc.rcv.num_handles += nhandles;
qla_rx_intr(ha, &sgc.rcv, sds_idx);
break;
case Q8_STAT_DESC_OPCODE_SGL_LRO:
desc_count =
Q8_STAT_DESC_COUNT_SGL_LRO((sdesc->data[1]));
if (desc_count > 1) {
c_idx = (comp_idx + desc_count -1) &
(NUM_STATUS_DESCRIPTORS-1);
sdesc0 = (q80_stat_desc_t *)
&hw->sds[sds_idx].sds_ring_base[c_idx];
if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) !=
Q8_STAT_DESC_OPCODE_CONT) {
desc_count = 0;
break;
}
}
bzero(&sgc, sizeof(qla_sgl_comp_t));
sgc.lro.payload_length =
Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV((sdesc->data[0]));
sgc.lro.rss_hash =
Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
sgc.lro.num_handles = 1;
sgc.lro.handle[0] =
Q8_STAT_DESC_HANDLE((sdesc->data[0]));
if (Q8_SGL_LRO_STAT_TS((sdesc->data[1])))
sgc.lro.flags |= Q8_LRO_COMP_TS;
if (Q8_SGL_LRO_STAT_PUSH_BIT((sdesc->data[1])))
sgc.lro.flags |= Q8_LRO_COMP_PUSH_BIT;
sgc.lro.l2_offset =
Q8_SGL_LRO_STAT_L2_OFFSET((sdesc->data[1]));
sgc.lro.l4_offset =
Q8_SGL_LRO_STAT_L4_OFFSET((sdesc->data[1]));
if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
sgc.lro.vlan_tag =
Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
}
QL_ASSERT(ha, (desc_count <= 7) ,\
("%s: [sds_idx, data0, data1]="\
"[%d, 0x%llx, 0x%llx]\n",\
__func__, sds_idx,\
(long long unsigned int)sdesc->data[0],\
(long long unsigned int)sdesc->data[1]));
if (qla_rcv_cont_sds(ha, sds_idx, comp_idx,
desc_count, &sgc.lro.handle[1], &nhandles)) {
device_printf(dev,
"%s: [sds_idx, data0, data1]="\
"[%d, 0x%llx, 0x%llx]\n",\
__func__, sds_idx,\
(long long unsigned int)sdesc->data[0],\
(long long unsigned int)sdesc->data[1]);
desc_count = 0;
break;
}
sgc.lro.num_handles += nhandles;
if (qla_lro_intr(ha, &sgc.lro, sds_idx)) {
device_printf(dev,
"%s: [sds_idx, data0, data1]="\
"[%d, 0x%llx, 0x%llx]\n",\
__func__, sds_idx,\
(long long unsigned int)sdesc->data[0],\
(long long unsigned int)sdesc->data[1]);
device_printf(dev,
"%s: [comp_idx, c_idx, dcount, nhndls]="\
"[%d, %d, %d, %d]\n",\
__func__, comp_idx, c_idx, desc_count,
sgc.lro.num_handles);
if (desc_count > 1) {
device_printf(dev,
"%s: [sds_idx, data0, data1]="\
"[%d, 0x%llx, 0x%llx]\n",\
__func__, sds_idx,\
(long long unsigned int)sdesc0->data[0],\
(long long unsigned int)sdesc0->data[1]);
}
}
break;
default:
device_printf(dev, "%s: default 0x%llx!\n", __func__,
(long long unsigned int)sdesc->data[0]);
break;
}
if (desc_count == 0)
break;
sds_replenish_threshold += desc_count;
while (desc_count--) {
sdesc->data[0] = 0ULL;
sdesc->data[1] = 0ULL;
comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
sdesc = (q80_stat_desc_t *)
&hw->sds[sds_idx].sds_ring_base[comp_idx];
}
if (sds_replenish_threshold > ha->hw.sds_cidx_thres) {
sds_replenish_threshold = 0;
if (hw->sds[sds_idx].sdsr_next != comp_idx) {
QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx,\
comp_idx);
}
hw->sds[sds_idx].sdsr_next = comp_idx;
}
}
if (ha->flags.stop_rcv)
goto qla_rcv_isr_exit;
if (hw->sds[sds_idx].sdsr_next != comp_idx) {
QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx, comp_idx);
}
hw->sds[sds_idx].sdsr_next = comp_idx;
sdesc = (q80_stat_desc_t *)&hw->sds[sds_idx].sds_ring_base[comp_idx];
opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
if (opcode)
ret = -1;
qla_rcv_isr_exit:
hw->sds[sds_idx].rcv_active = 0;
return (ret);
}
void
ql_mbx_isr(void *arg)
{
qla_host_t *ha;
uint32_t data;
uint32_t prev_link_state;
ha = arg;
if (ha == NULL) {
device_printf(ha->pci_dev, "%s: arg == NULL\n", __func__);
return;
}
data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
if ((data & 0x3) != 0x1) {
WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0);
return;
}
data = READ_REG32(ha, Q8_FW_MBOX0);
if ((data & 0xF000) != 0x8000)
return;
data = data & 0xFFFF;
switch (data) {
case 0x8001: /* It's an AEN */
ha->hw.cable_oui = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
data = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
ha->hw.cable_length = data & 0xFFFF;
data = data >> 16;
ha->hw.link_speed = data & 0xFFF;
data = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
prev_link_state = ha->hw.link_up;
ha->hw.link_up = (((data & 0xFF) == 0) ? 0 : 1);
if (prev_link_state != ha->hw.link_up) {
if (ha->hw.link_up)
if_link_state_change(ha->ifp, LINK_STATE_UP);
else
if_link_state_change(ha->ifp, LINK_STATE_DOWN);
}
ha->hw.module_type = ((data >> 8) & 0xFF);
ha->hw.flags.fduplex = (((data & 0xFF0000) == 0) ? 0 : 1);
ha->hw.flags.autoneg = (((data & 0xFF000000) == 0) ? 0 : 1);
data = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
ha->hw.flags.loopback_mode = data & 0x03;
ha->hw.link_faults = (data >> 3) & 0xFF;
WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
break;
default:
device_printf(ha->pci_dev, "%s: AEN[0x%08x]\n", __func__, data);
WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
break;
}
return;
}
static void
qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp, uint32_t r_idx)
{
qla_rx_buf_t *rxb;
int count = sdsp->rx_free;
uint32_t rx_next;
qla_rdesc_t *rdesc;
/* we can play with this value via a sysctl */
uint32_t replenish_thresh = ha->hw.rds_pidx_thres;
rdesc = &ha->hw.rds[r_idx];
rx_next = rdesc->rx_next;
while (count--) {
rxb = sdsp->rxb_free;
if (rxb == NULL)
break;
sdsp->rxb_free = rxb->next;
sdsp->rx_free--;
if (ql_get_mbuf(ha, rxb, NULL) == 0) {
qla_set_hw_rcv_desc(ha, r_idx, rdesc->rx_in,
rxb->handle,
rxb->paddr, (rxb->m_head)->m_pkthdr.len);
rdesc->rx_in++;
if (rdesc->rx_in == NUM_RX_DESCRIPTORS)
rdesc->rx_in = 0;
rdesc->rx_next++;
if (rdesc->rx_next == NUM_RX_DESCRIPTORS)
rdesc->rx_next = 0;
} else {
device_printf(ha->pci_dev,
"%s: ql_get_mbuf [0,(%d),(%d)] failed\n",
__func__, rdesc->rx_in, rxb->handle);
rxb->m_head = NULL;
rxb->next = sdsp->rxb_free;
sdsp->rxb_free = rxb;
sdsp->rx_free++;
break;
}
if (replenish_thresh-- == 0) {
QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,
rdesc->rx_next);
rx_next = rdesc->rx_next;
replenish_thresh = ha->hw.rds_pidx_thres;
}
}
if (rx_next != rdesc->rx_next) {
QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,
rdesc->rx_next);
}
}
void
ql_isr(void *arg)
{
qla_ivec_t *ivec = arg;
qla_host_t *ha ;
int idx;
qla_hw_t *hw;
struct ifnet *ifp;
uint32_t data = 0;
uint32_t ret = 0;
ha = ivec->ha;
hw = &ha->hw;
ifp = ha->ifp;
if ((idx = ivec->sds_idx) >= ha->hw.num_sds_rings)
return;
if (idx == 0)
taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
data = READ_REG32(ha, ha->hw.intr_src[idx]);
if (data & 0x1 )
ret = qla_rcv_isr(ha, idx, -1);
if (idx == 0)
taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
if (!ha->flags.stop_rcv) {
QL_ENABLE_INTERRUPTS(ha, idx);
}
return;
}

1304
sys/dev/qlxgbe/ql_misc.c Normal file
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1703
sys/dev/qlxgbe/ql_os.c Normal file
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File diff suppressed because it is too large Load Diff

170
sys/dev/qlxgbe/ql_os.h Normal file
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@ -0,0 +1,170 @@
/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: ql_os.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QL_OS_H_
#define _QL_OS_H_
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/mbuf.h>
#include <sys/protosw.h>
#include <sys/socket.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/kernel.h>
#include <sys/sockio.h>
#include <sys/types.h>
#include <machine/atomic.h>
#include <machine/_inttypes.h>
#include <sys/conf.h>
#if __FreeBSD_version < 900044
#error FreeBSD Version not supported - use version >= 900044
#endif
#include <net/if.h>
#include <net/if_arp.h>
#include <net/ethernet.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/bpf.h>
#include <net/if_types.h>
#include <net/if_vlan_var.h>
#include <netinet/in_systm.h>
#include <netinet/in.h>
#include <netinet/if_ether.h>
#include <netinet/ip.h>
#include <netinet/ip6.h>
#include <netinet/tcp.h>
#include <netinet/udp.h>
#include <netinet/in_var.h>
#include <netinet/tcp_lro.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <sys/mutex.h>
#include <sys/condvar.h>
#include <sys/proc.h>
#include <sys/sysctl.h>
#include <sys/endian.h>
#include <sys/taskqueue.h>
#include <sys/pcpu.h>
#include <sys/unistd.h>
#include <sys/kthread.h>
#define QLA_USEC_DELAY(usec) DELAY(usec)
static __inline int qla_ms_to_hz(int ms)
{
int qla_hz;
struct timeval t;
t.tv_sec = ms / 1000;
t.tv_usec = (ms % 1000) * 1000;
qla_hz = tvtohz(&t);
if (qla_hz < 0)
qla_hz = 0x7fffffff;
if (!qla_hz)
qla_hz = 1;
return (qla_hz);
}
static __inline int qla_sec_to_hz(int sec)
{
struct timeval t;
t.tv_sec = sec;
t.tv_usec = 0;
return (tvtohz(&t));
}
#define qla_host_to_le16(x) htole16(x)
#define qla_host_to_le32(x) htole32(x)
#define qla_host_to_le64(x) htole64(x)
#define qla_host_to_be16(x) htobe16(x)
#define qla_host_to_be32(x) htobe32(x)
#define qla_host_to_be64(x) htobe64(x)
#define qla_le16_to_host(x) le16toh(x)
#define qla_le32_to_host(x) le32toh(x)
#define qla_le64_to_host(x) le64toh(x)
#define qla_be16_to_host(x) be16toh(x)
#define qla_be32_to_host(x) be32toh(x)
#define qla_be64_to_host(x) be64toh(x)
MALLOC_DECLARE(M_QLA83XXBUF);
#define qla_mdelay(fn, msecs) \
{\
if (cold) \
DELAY((msecs * 1000)); \
else \
pause(fn, qla_ms_to_hz(msecs)); \
}
/*
* Locks
*/
#define QLA_LOCK(ha, str, no_delay) qla_lock(ha, str, no_delay)
#define QLA_UNLOCK(ha, str) qla_unlock(ha, str)
#define QLA_TX_LOCK(ha) mtx_lock(&ha->tx_lock);
#define QLA_TX_UNLOCK(ha) mtx_unlock(&ha->tx_lock);
/*
* structure encapsulating a DMA buffer
*/
struct qla_dma {
bus_size_t alignment;
uint32_t size;
void *dma_b;
bus_addr_t dma_addr;
bus_dmamap_t dma_map;
bus_dma_tag_t dma_tag;
};
typedef struct qla_dma qla_dma_t;
#endif /* #ifndef _QL_OS_H_ */

1409
sys/dev/qlxgbe/ql_reset.c Normal file
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147
sys/dev/qlxgbe/ql_tmplt.h Normal file
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@ -0,0 +1,147 @@
/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: ql_tmplt.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QL_TMPLT_H_
#define _QL_TMPLT_H_
typedef struct _q8_tmplt_hdr {
uint16_t version;
uint16_t signature;
uint16_t size;
uint16_t nentries;
uint16_t stop_seq_off;
uint16_t csum;
uint16_t init_seq_off;
uint16_t start_seq_off;
} __packed q8_tmplt_hdr_t;
typedef struct _q8_ce_hdr {
uint16_t opcode;
uint16_t size;
uint16_t opcount;
uint16_t delay_to;
} __packed q8_ce_hdr_t;
/*
* Values for opcode field in q8_ce_hdr_t
*/
#define Q8_CE_OPCODE_NOP 0x000
#define Q8_CE_OPCODE_WRITE_LIST 0x001
#define Q8_CE_OPCODE_READ_WRITE_LIST 0x002
#define Q8_CE_OPCODE_POLL_LIST 0x004
#define Q8_CE_OPCODE_POLL_WRITE_LIST 0x008
#define Q8_CE_OPCODE_READ_MODIFY_WRITE 0x010
#define Q8_CE_OPCODE_SEQ_PAUSE 0x020
#define Q8_CE_OPCODE_SEQ_END 0x040
#define Q8_CE_OPCODE_TMPLT_END 0x080
#define Q8_CE_OPCODE_POLL_RD_LIST 0x100
/*
* structure for Q8_CE_OPCODE_WRITE_LIST
*/
typedef struct _q8_wrl_e {
uint32_t addr;
uint32_t value;
} __packed q8_wrl_e_t;
/*
* structure for Q8_CE_OPCODE_READ_WRITE_LIST
*/
typedef struct _q8_rdwrl_e {
uint32_t rd_addr;
uint32_t wr_addr;
} __packed q8_rdwrl_e_t;
/*
* common for
* Q8_CE_OPCODE_POLL_LIST
* Q8_CE_OPCODE_POLL_WRITE_LIST
* Q8_CE_OPCODE_POLL_RD_LIST
*/
typedef struct _q8_poll_hdr {
uint32_t tmask;
uint32_t tvalue;
} q8_poll_hdr_t;
/*
* structure for Q8_CE_OPCODE_POLL_LIST
*/
typedef struct _q8_poll_e {
uint32_t addr;
uint32_t to_addr;
} q8_poll_e_t;
/*
* structure for Q8_CE_OPCODE_POLL_WRITE_LIST
*/
typedef struct _q8_poll_wr_e {
uint32_t dr_addr;
uint32_t dr_value;
uint32_t ar_addr;
uint32_t ar_value;
} q8_poll_wr_e_t;
/*
* structure for Q8_CE_OPCODE_POLL_RD_LIST
*/
typedef struct _q8_poll_rd_e {
uint32_t ar_addr;
uint32_t ar_value;
uint32_t dr_addr;
uint32_t rsrvd;
} q8_poll_rd_e_t;
/*
* structure for Q8_CE_OPCODE_READ_MODIFY_WRITE
*/
typedef struct _q8_rdmwr_hdr {
uint32_t and_value;
uint32_t xor_value;
uint32_t or_value;
uint8_t shl;
uint8_t shr;
uint8_t index_a;
uint8_t rsrvd;
} q8_rdmwr_hdr_t;
typedef struct _q8_rdmwr_e {
uint32_t rd_addr;
uint32_t wr_addr;
} q8_rdmwr_e_t;
extern unsigned char ql83xx_resetseq[];
extern unsigned int ql83xx_resetseq_len;
#endif /* #ifndef _QL_TMPLT_H_ */

41
sys/dev/qlxgbe/ql_ver.h Normal file
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@ -0,0 +1,41 @@
/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: ql_ver.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QL_VER_H_
#define _QL_VER_H_
#define QLA_VERSION_MAJOR 3
#define QLA_VERSION_MINOR 10
#define QLA_VERSION_BUILD 10
#endif /* #ifndef _QL_VER_H_ */

2
sys/modules/Makefile
View File

@ -271,6 +271,7 @@ SUBDIR= \
pty \
puc \
${_qlxgb} \
${_qlxgbe} \
ral \
${_ralfw} \
${_random} \
@ -710,6 +711,7 @@ _padlock= padlock
.endif
_pccard= pccard
_qlxgb= qlxgb
_qlxgbe= qlxgbe
_rdma= rdma
_s3= s3
_safe= safe

50
sys/modules/qlxgbe/Makefile Normal file
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@ -0,0 +1,50 @@
#/*
# * Copyright (c) 2011-2012 Qlogic Corporation
# * All rights reserved.
# *
# * Redistribution and use in source and binary forms, with or without
# * modification, are permitted provided that the following conditions
# * are met:
# *
# * 1. Redistributions of source code must retain the above copyright
# * notice, this list of conditions and the following disclaimer.
# * 2. Redistributions in binary form must reproduce the above copyright
# * notice, this list of conditions and the following disclaimer in the
# * documentation and/or other materials provided with the distribution.
# *
# * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
# * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# * POSSIBILITY OF SUCH DAMAGE.
# */
#/*
# * File : Makefile
# * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
# */
#
# $FreeBSD$
#
.PATH: ${.CURDIR}/../../dev/qlxgbe
KMOD=if_qlxgbe
SRCS=ql_os.c ql_dbg.c ql_hw.c ql_misc.c ql_isr.c ql_ioctl.c
SRCS+= ql_reset.c
SRCS+= device_if.h bus_if.h pci_if.h
#CFLAGS += -DQL_DBG
clean:
rm -f opt_bdg.h device_if.h bus_if.h pci_if.h export_syms
rm -f *.o *.kld *.ko
rm -f @ machine x86
.include <bsd.kmod.mk>