Rudimentary AER reading code for ddb(4).
This is very primitive code to inspect the PCI error state and AER error state, dump the log and clear errors, from ddb. pci_print_faulted_dev() is made external to allow calling it from other places. It was called from NMI handler but this chunk is not included. Also there is a tunable-controlled code to clear AER on device attach, disabled by default. All this code was useful to me when I debugged ACPI_DMAR failures (not faults) long time ago. Reviewed by: cem, imp (previous version) Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D7813
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kib
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5f8e558a6b
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@ -399,6 +399,11 @@ static int pci_enable_ari = 1;
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SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari,
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0, "Enable support for PCIe Alternative RID Interpretation");
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static int pci_clear_aer_on_attach = 0;
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SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN,
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&pci_clear_aer_on_attach, 0,
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"Clear port and device AER state on driver attach");
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static int
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pci_has_quirk(uint32_t devid, int quirk)
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{
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@ -4204,17 +4209,98 @@ pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid,
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}
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#endif
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static void
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pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo)
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{
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int aer;
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uint32_t r;
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uint16_t r2;
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if (dinfo->cfg.pcie.pcie_location != 0 &&
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dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) {
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r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
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PCIER_ROOT_CTL, 2);
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r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR |
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PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL);
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pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
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PCIER_ROOT_CTL, r2, 2);
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}
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if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
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r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
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pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
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if (r != 0 && bootverbose) {
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pci_printf(&dinfo->cfg,
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"clearing AER UC 0x%08x -> 0x%08x\n",
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r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS,
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4));
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}
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r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4);
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r &= ~(PCIM_AER_UC_TRAINING_ERROR |
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PCIM_AER_UC_DL_PROTOCOL_ERROR |
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PCIM_AER_UC_SURPRISE_LINK_DOWN |
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PCIM_AER_UC_POISONED_TLP |
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PCIM_AER_UC_FC_PROTOCOL_ERROR |
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PCIM_AER_UC_COMPLETION_TIMEOUT |
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PCIM_AER_UC_COMPLETER_ABORT |
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PCIM_AER_UC_UNEXPECTED_COMPLETION |
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PCIM_AER_UC_RECEIVER_OVERFLOW |
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PCIM_AER_UC_MALFORMED_TLP |
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PCIM_AER_UC_ECRC_ERROR |
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PCIM_AER_UC_UNSUPPORTED_REQUEST |
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PCIM_AER_UC_ACS_VIOLATION |
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PCIM_AER_UC_INTERNAL_ERROR |
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PCIM_AER_UC_MC_BLOCKED_TLP |
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PCIM_AER_UC_ATOMIC_EGRESS_BLK |
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PCIM_AER_UC_TLP_PREFIX_BLOCKED);
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pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4);
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r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
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pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
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if (r != 0 && bootverbose) {
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pci_printf(&dinfo->cfg,
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"clearing AER COR 0x%08x -> 0x%08x\n",
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r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS,
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4));
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}
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r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4);
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r &= ~(PCIM_AER_COR_RECEIVER_ERROR |
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PCIM_AER_COR_BAD_TLP |
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PCIM_AER_COR_BAD_DLLP |
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PCIM_AER_COR_REPLAY_ROLLOVER |
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PCIM_AER_COR_REPLAY_TIMEOUT |
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PCIM_AER_COR_ADVISORY_NF_ERROR |
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PCIM_AER_COR_INTERNAL_ERROR |
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PCIM_AER_COR_HEADER_LOG_OVFLOW);
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pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4);
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r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
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PCIER_DEVICE_CTL, 2);
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r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE |
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PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE;
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pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
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PCIER_DEVICE_CTL, r, 2);
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}
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}
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void
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pci_add_child(device_t bus, struct pci_devinfo *dinfo)
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{
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dinfo->cfg.dev = device_add_child(bus, NULL, -1);
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device_set_ivars(dinfo->cfg.dev, dinfo);
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device_t dev;
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dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1);
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device_set_ivars(dev, dinfo);
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resource_list_init(&dinfo->resources);
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pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
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pci_cfg_restore(dinfo->cfg.dev, dinfo);
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pci_cfg_save(dev, dinfo, 0);
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pci_cfg_restore(dev, dinfo);
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pci_print_verbose(dinfo);
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pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
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pci_add_resources(bus, dev, 0, 0);
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pci_child_added(dinfo->cfg.dev);
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if (pci_clear_aer_on_attach)
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pci_add_child_clear_aer(dev, dinfo);
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EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev);
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}
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@ -6280,3 +6366,128 @@ pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt)
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}
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return (NULL);
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}
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static void
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pci_print_faulted_dev_name(const struct pci_devinfo *dinfo)
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{
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const char *dev_name;
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device_t dev;
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dev = dinfo->cfg.dev;
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printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus,
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dinfo->cfg.slot, dinfo->cfg.func);
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dev_name = device_get_name(dev);
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if (dev_name != NULL)
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printf(" (%s%d)", dev_name, device_get_unit(dev));
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}
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void
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pci_print_faulted_dev(void)
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{
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struct pci_devinfo *dinfo;
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device_t dev;
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int aer, i;
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uint32_t r1, r2;
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uint16_t status;
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STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
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dev = dinfo->cfg.dev;
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status = pci_read_config(dev, PCIR_STATUS, 2);
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status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT |
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PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT |
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PCIM_STATUS_SERR | PCIM_STATUS_PERR;
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if (status != 0) {
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pci_print_faulted_dev_name(dinfo);
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printf(" error 0x%04x\n", status);
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}
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if (dinfo->cfg.pcie.pcie_location != 0) {
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status = pci_read_config(dev,
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dinfo->cfg.pcie.pcie_location +
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PCIER_DEVICE_STA, 2);
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if ((status & (PCIEM_STA_CORRECTABLE_ERROR |
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PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
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PCIEM_STA_UNSUPPORTED_REQ)) != 0) {
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pci_print_faulted_dev_name(dinfo);
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printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n",
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pci_read_config(dev,
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dinfo->cfg.pcie.pcie_location +
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PCIER_DEVICE_CTL, 2),
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status);
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}
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}
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if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
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r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
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r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
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if (r1 != 0 || r2 != 0) {
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pci_print_faulted_dev_name(dinfo);
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printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n"
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" COR 0x%08x Mask 0x%08x Ctl 0x%08x\n",
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r1, pci_read_config(dev, aer +
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PCIR_AER_UC_MASK, 4),
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pci_read_config(dev, aer +
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PCIR_AER_UC_SEVERITY, 4),
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r2, pci_read_config(dev, aer +
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PCIR_AER_COR_MASK, 4),
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pci_read_config(dev, aer +
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PCIR_AER_CAP_CONTROL, 4));
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for (i = 0; i < 4; i++) {
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r1 = pci_read_config(dev, aer +
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PCIR_AER_HEADER_LOG + i * 4, 4);
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printf(" HL%d: 0x%08x\n", i, r1);
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}
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}
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}
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}
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}
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#ifdef DDB
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DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db)
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{
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pci_print_faulted_dev();
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}
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static void
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db_clear_pcie_errors(const struct pci_devinfo *dinfo)
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{
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device_t dev;
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int aer;
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uint32_t r;
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dev = dinfo->cfg.dev;
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r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
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PCIER_DEVICE_STA, 2);
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pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
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PCIER_DEVICE_STA, r, 2);
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if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0)
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return;
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r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
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if (r != 0)
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pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
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r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
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if (r != 0)
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pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
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}
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DB_COMMAND(pci_clearerr, db_pci_clearerr)
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{
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struct pci_devinfo *dinfo;
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device_t dev;
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uint16_t status, status1;
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STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
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dev = dinfo->cfg.dev;
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status1 = status = pci_read_config(dev, PCIR_STATUS, 2);
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status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT |
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PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT |
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PCIM_STATUS_SERR | PCIM_STATUS_PERR;
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if (status1 != 0) {
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status &= ~status1;
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pci_write_config(dev, PCIR_STATUS, status, 2);
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}
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if (dinfo->cfg.pcie.pcie_location != 0)
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db_clear_pcie_errors(dinfo);
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}
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}
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#endif
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@ -682,6 +682,8 @@ bool pcie_flr(device_t dev, u_int max_delay, bool force);
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int pcie_get_max_completion_timeout(device_t dev);
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bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay);
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void pci_print_faulted_dev(void);
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#ifdef BUS_SPACE_MAXADDR
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#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
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#define PCI_DMA_BOUNDARY 0x100000000
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