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Add some new fields and bits from NVMe 1.4.

Browse Source 
MFC after:	2 weeks
Sponsored by:	iXsystems, Inc.
This commit is contained in:
mav 2019-07-29 03:28:46 +00:00
parent 6c26c4da8f
commit f13299f219
2 changed files with 176 additions and 15 deletions
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37
sbin/nvmecontrol/identify_ext.c
View File

@ -49,7 +49,7 @@ nvme_print_controller(struct nvme_controller_data *cdata)
uint8_t str[128];
char cbuf[UINT128_DIG + 1];
uint16_t oncs, oacs;
uint8_t compare, write_unc, dsm, vwc_present;
uint8_t compare, write_unc, dsm, t;
uint8_t security, fmt, fw, nsmgmt;
uint8_t fw_slot1_ro, fw_num_slots;
uint8_t ns_smart;
@ -63,8 +63,6 @@ nvme_print_controller(struct nvme_controller_data *cdata)
NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK;
dsm = (oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) &
NVME_CTRLR_DATA_ONCS_DSM_MASK;
vwc_present = (cdata->vwc >> NVME_CTRLR_DATA_VWC_PRESENT_SHIFT) &
NVME_CTRLR_DATA_VWC_PRESENT_MASK;
oacs = cdata->oacs;
security = (oacs >> NVME_CTRLR_DATA_OACS_SECURITY_SHIFT) &
@ -107,8 +105,10 @@ nvme_print_controller(struct nvme_controller_data *cdata)
printf("Recommended Arb Burst: %d\n", cdata->rab);
printf("IEEE OUI Identifier: %02x %02x %02x\n",
cdata->ieee[0], cdata->ieee[1], cdata->ieee[2]);
printf("Multi-Path I/O Capabilities: %s%s%s%s\n",
printf("Multi-Path I/O Capabilities: %s%s%s%s%s\n",
(cdata->mic == 0) ? "Not Supported" : "",
((cdata->mic >> NVME_CTRLR_DATA_MIC_ANAR_SHIFT) &
NVME_CTRLR_DATA_MIC_SRIOVVF_MASK) ? "Asymmetric, " : "",
((cdata->mic >> NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT) &
NVME_CTRLR_DATA_MIC_SRIOVVF_MASK) ? "SR-IOV VF, " : "",
((cdata->mic >> NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT) &
@ -149,9 +149,24 @@ nvme_print_controller(struct nvme_controller_data *cdata)
printf("Virtualization Management: %sSupported\n",
((oacs >> NVME_CTRLR_DATA_OACS_VM_SHIFT) &
NVME_CTRLR_DATA_OACS_VM_MASK) ? "" : "Not ");
printf("Doorbell Buffer Config %sSupported\n",
printf("Doorbell Buffer Config: %sSupported\n",
((oacs >> NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT) &
NVME_CTRLR_DATA_OACS_DBBUFFER_MASK) ? "" : "Not ");
printf("Get LBA Status: %sSupported\n",
((oacs >> NVME_CTRLR_DATA_OACS_GETLBA_SHIFT) &
NVME_CTRLR_DATA_OACS_GETLBA_MASK) ? "" : "Not ");
printf("Sanitize: ");
if (cdata->sanicap != 0) {
printf("%s%s%s\n",
((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_CES_SHIFT) &
NVME_CTRLR_DATA_SANICAP_CES_SHIFT) ? "crypto, " : "",
((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_BES_SHIFT) &
NVME_CTRLR_DATA_SANICAP_BES_SHIFT) ? "block, " : "",
((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_OWS_SHIFT) &
NVME_CTRLR_DATA_SANICAP_OWS_SHIFT) ? "overwrite" : "");
} else {
printf("Not Supported\n");
}
printf("Abort Command Limit: %d\n", cdata->acl+1);
printf("Async Event Request Limit: %d\n", cdata->aerl+1);
printf("Number of Firmware Slots: ");
@ -197,6 +212,9 @@ nvme_print_controller(struct nvme_controller_data *cdata)
printf("Timestamp feature: %sSupported\n",
((oncs >> NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT) &
NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK) ? "" : "Not ");
printf("Verify feature: %sSupported\n",
((oncs >> NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT) &
NVME_CTRLR_DATA_ONCS_VERIFY_MASK) ? "" : "Not ");
printf("Fused Operation Support: %s%s\n",
(cdata->fuses == 0) ? "Not Supported" : "",
((cdata->fuses >> NVME_CTRLR_DATA_FUSES_CNW_SHIFT) &
@ -208,8 +226,13 @@ nvme_print_controller(struct nvme_controller_data *cdata)
NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK) ? "All-NVM" : "Per-NS",
((cdata->fna >> NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT) &
NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK) ? "All-NVM" : "Per-NS");
printf("Volatile Write Cache: %s\n",
vwc_present ? "Present" : "Not Present");
t = (cdata->vwc >> NVME_CTRLR_DATA_VWC_ALL_SHIFT) &
NVME_CTRLR_DATA_VWC_ALL_MASK;
printf("Volatile Write Cache: %s%s\n",
((cdata->vwc >> NVME_CTRLR_DATA_VWC_PRESENT_SHIFT) &
NVME_CTRLR_DATA_VWC_PRESENT_MASK) ? "Present" : "Not Present",
(t == NVME_CTRLR_DATA_VWC_ALL_NO) ? ", no flush all" :
(t == NVME_CTRLR_DATA_VWC_ALL_YES) ? ", flush all" : "");
if (nsmgmt) {
printf("\n");

154
sys/dev/nvme/nvme.h
View File

@ -175,6 +175,9 @@
/* SR-IOV Virtual Function */
#define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2)
#define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1)
/* Asymmetric Namespace Access Reporting */
#define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3)
#define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1)
/** OACS - optional admin command support */
/* supports security send/receive commands */
@ -204,6 +207,9 @@
/* supports Doorbell Buffer Config */
#define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8)
#define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1)
/* supports Get LBA Status */
#define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9)
#define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1)
/** firmware updates */
/* first slot is read-only */
@ -212,6 +218,9 @@
/* number of firmware slots */
#define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1)
#define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7)
/* firmware activation without reset */
#define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4)
#define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1)
/** log page attributes */
/* per namespace smart/health log page */
@ -228,6 +237,26 @@
#define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0)
#define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1)
/** Sanitize Capabilities */
/* Crypto Erase Support */
#define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0)
#define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1)
/* Block Erase Support */
#define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1)
#define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1)
/* Overwrite Support */
#define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2)
#define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1)
/* No-Deallocate Inhibited */
#define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29)
#define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1)
/* No-Deallocate Modifies Media After Sanitize */
#define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30)
#define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3)
#define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0)
#define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1)
#define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2)
/** submission queue entry size */
#define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0)
#define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF)
@ -255,6 +284,8 @@
#define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1)
#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6)
#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1)
#define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7)
#define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1)
/** Fused Operation Support */
#define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0)
@ -269,8 +300,15 @@
#define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1)
/** volatile write cache */
/* volatile write cache present */
#define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0)
#define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1)
/* flush all namespaces supported */
#define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1)
#define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3)
#define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0)
#define NVME_CTRLR_DATA_VWC_ALL_NO (2)
#define NVME_CTRLR_DATA_VWC_ALL_YES (3)
/** namespace features */
/* thin provisioning */
@ -285,6 +323,9 @@
/* NGUID and EUI64 fields are not reusable */
#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3)
#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1)
/* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
#define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4)
#define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1)
/** formatted lba size */
#define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0)
@ -793,12 +834,27 @@ struct nvme_controller_data {
/** Controller Attributes */
uint32_t ctratt; /* bitfield really */
uint8_t reserved1[12];
/** Read Recovery Levels Supported */
uint16_t rrls;
uint8_t reserved1[9];
/** Controller Type */
uint8_t cntrltype;
/** FRU Globally Unique Identifier */
uint8_t fguid[16];
uint8_t reserved2[128];
/** Command Retry Delay Time 1 */
uint16_t crdt1;
/** Command Retry Delay Time 2 */
uint16_t crdt2;
/** Command Retry Delay Time 3 */
uint16_t crdt3;
uint8_t reserved2[122];
/* bytes 256-511: admin command set attributes */
@ -878,7 +934,34 @@ struct nvme_controller_data {
/** Sanitize Capabilities */
uint32_t sanicap; /* Really a bitfield */
uint8_t reserved3[180];
/** Host Memory Buffer Minimum Descriptor Entry Size */
uint32_t hmminds;
/** Host Memory Maximum Descriptors Entries */
uint16_t hmmaxd;
/** NVM Set Identifier Maximum */
uint16_t nsetidmax;
/** Endurance Group Identifier Maximum */
uint16_t endgidmax;
/** ANA Transition Time */
uint8_t anatt;
/** Asymmetric Namespace Access Capabilities */
uint8_t anacap;
/** ANA Group Identifier Maximum */
uint32_t anagrpmax;
/** Number of ANA Group Identifiers */
uint32_t nanagrpid;
/** Persistent Event Log Size */
uint32_t pels;
uint8_t reserved3[156];
/* bytes 512-703: nvm command set attributes */
/** submission queue entry size */
@ -913,7 +996,9 @@ struct nvme_controller_data {
/** NVM Vendor Specific Command Configuration */
uint8_t nvscc;
uint8_t reserved5;
/** Namespace Write Protection Capabilities */
uint8_t nwpc;
/** Atomic Compare & Write Unit */
uint16_t acwu;
@ -922,8 +1007,11 @@ struct nvme_controller_data {
/** SGL Support */
uint32_t sgls;
/** Maximum Number of Allowed Namespaces */
uint32_t mnan;
/* bytes 540-767: Reserved */
uint8_t reserved7[228];
uint8_t reserved7[224];
/** NVM Subsystem NVMe Qualified Name */
uint8_t subnqn[256];
@ -1008,8 +1096,38 @@ struct nvme_namespace_data {
/** NVM Capacity */
uint8_t nvmcap[16];
/* bytes 64-103: Reserved */
uint8_t reserved5[40];
/** Namespace Preferred Write Granularity */
uint16_t npwg;
/** Namespace Preferred Write Alignment */
uint16_t npwa;
/** Namespace Preferred Deallocate Granularity */
uint16_t npdg;
/** Namespace Preferred Deallocate Alignment */
uint16_t npda;
/** Namespace Optimal Write Size */
uint16_t nows;
/* bytes 74-91: Reserved */
uint8_t reserved5[18];
/** ANA Group Identifier */
uint32_t anagrpid;
/* bytes 96-98: Reserved */
uint8_t reserved6[3];
/** Namespace Attributes */
uint8_t nsattr;
/** NVM Set Identifier */
uint16_t nvmsetid;
/** Endurance Group Identifier */
uint16_t endgid;
/** Namespace Globally Unique Identifier */
uint8_t nguid[16];
@ -1020,7 +1138,7 @@ struct nvme_namespace_data {
/** lba format support */
uint32_t lbaf[16];
uint8_t reserved6[192];
uint8_t reserved7[192];
uint8_t vendor_specific[3712];
} __packed __aligned(4);
@ -1402,6 +1520,10 @@ void nvme_controller_data_swapbytes(struct nvme_controller_data *s)
s->rtd3e = le32toh(s->rtd3e);
s->oaes = le32toh(s->oaes);
s->ctratt = le32toh(s->ctratt);
s->rrls = le16toh(s->rrls);
s->crdt1 = le16toh(s->crdt1);
s->crdt2 = le16toh(s->crdt2);
s->crdt3 = le16toh(s->crdt3);
s->oacs = le16toh(s->oacs);
s->wctemp = le16toh(s->wctemp);
s->cctemp = le16toh(s->cctemp);
@ -1415,6 +1537,13 @@ void nvme_controller_data_swapbytes(struct nvme_controller_data *s)
s->mntmt = le16toh(s->mntmt);
s->mxtmt = le16toh(s->mxtmt);
s->sanicap = le32toh(s->sanicap);
s->hmminds = le32toh(s->hmminds);
s->hmmaxd = le16toh(s->hmmaxd);
s->nsetidmax = le16toh(s->nsetidmax);
s->endgidmax = le16toh(s->endgidmax);
s->anagrpmax = le32toh(s->anagrpmax);
s->nanagrpid = le32toh(s->nanagrpid);
s->pels = le32toh(s->pels);
s->maxcmd = le16toh(s->maxcmd);
s->nn = le32toh(s->nn);
s->oncs = le16toh(s->oncs);
@ -1423,6 +1552,7 @@ void nvme_controller_data_swapbytes(struct nvme_controller_data *s)
s->awupf = le16toh(s->awupf);
s->acwu = le16toh(s->acwu);
s->sgls = le32toh(s->sgls);
s->mnan = le32toh(s->mnan);
for (i = 0; i < 32; i++)
nvme_power_state_swapbytes(&s->power_state[i]);
}
@ -1442,6 +1572,14 @@ void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s)
s->nabo = le16toh(s->nabo);
s->nabspf = le16toh(s->nabspf);
s->noiob = le16toh(s->noiob);
s->npwg = le16toh(s->npwg);
s->npwa = le16toh(s->npwa);
s->npdg = le16toh(s->npdg);
s->npda = le16toh(s->npda);
s->nows = le16toh(s->nows);
s->anagrpid = le32toh(s->anagrpid);
s->nvmsetid = le16toh(s->nvmsetid);
s->endgid = le16toh(s->endgid);
for (i = 0; i < 16; i++)
s->lbaf[i] = le32toh(s->lbaf[i]);
}