Explicitly enable I/O and memory decoding in the bridge's command register
when activating an I/O or memory window on the CardBus bridge. Tested by: Olivier Cochard-Labbe <olivier@cochard.me> Reviewed by: imp MFC after: 3 days
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@ -1038,6 +1038,13 @@ cbb_cardbus_power_disable_socket(device_t brdev, device_t child)
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/* CardBus Resource */
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/* CardBus Resource */
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/************************************************************************/
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/************************************************************************/
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static void
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cbb_activate_window(device_t brdev, int type)
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{
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PCI_ENABLE_IO(device_get_parent(brdev), brdev, type);
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}
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static int
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static int
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cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end)
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cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end)
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{
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{
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@ -1055,6 +1062,7 @@ cbb_cardbus_io_open(device_t brdev, int win, uint32_t start, uint32_t end)
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pci_write_config(brdev, basereg, start, 4);
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pci_write_config(brdev, basereg, start, 4);
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pci_write_config(brdev, limitreg, end, 4);
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pci_write_config(brdev, limitreg, end, 4);
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cbb_activate_window(brdev, SYS_RES_IOPORT);
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return (0);
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return (0);
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}
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}
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@ -1075,6 +1083,7 @@ cbb_cardbus_mem_open(device_t brdev, int win, uint32_t start, uint32_t end)
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pci_write_config(brdev, basereg, start, 4);
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pci_write_config(brdev, basereg, start, 4);
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pci_write_config(brdev, limitreg, end, 4);
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pci_write_config(brdev, limitreg, end, 4);
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cbb_activate_window(brdev, SYS_RES_MEMORY);
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return (0);
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return (0);
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}
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}
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@ -1342,7 +1351,12 @@ cbb_pcic_activate_resource(device_t brdev, device_t child, int type, int rid,
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struct resource *res)
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struct resource *res)
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{
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{
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struct cbb_softc *sc = device_get_softc(brdev);
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struct cbb_softc *sc = device_get_softc(brdev);
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return (exca_activate_resource(&sc->exca[0], child, type, rid, res));
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int error;
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error = exca_activate_resource(&sc->exca[0], child, type, rid, res);
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if (error == 0)
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cbb_activate_window(brdev, type);
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return (error);
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}
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}
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static int
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static int
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