It turns out that checking the first DWORD register is more reliable
on a variety of cards. Adjust the comments accordingly to match the code. Even if the vendor chose 0xffff for the device ID, the vendor ID can't be 0xffff, so the test is still valid from a standards perspective.
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9db87c45ee
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@ -946,19 +946,21 @@ cbb_cardbus_reset(device_t brdev, int on)
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*/
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if (on && CBB_CARD_PRESENT(cbb_get(sc, CBB_SOCKET_STATE))) {
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/*
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* After clearing reset, wait up to 1.1s for the vendor of
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* device 0.0 to become != 0xffff. The PCMCIA PC Card Host
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* System Specification says that when powering up the card,
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* the PCI Spec v2.1 must be followed. In PCI spec v2.2 Table
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* 4-6, Trhfa (Reset High to first Config Access) is at most
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* 2^25 clocks, or just over 1s. Secont 2.2.1 states any card
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* not ready to participate in bus transactions must tristate
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* its outputs. Therefore, any access to its configuration
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* registers must be ignored. In that state, the vendor will
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* read 0xffff. Section 6.2.1 states a vendor id of 0xffff is
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* invalid, so this can never match a real card. Print a
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* warning if it never returns a real id. The PCMCIA PC Card
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* Electrical Spec Section 5.2.7.1 implies only device 0.
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* After clearing reset, wait up to 1.1s for the first
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* configuration register (vendor/product) configuration
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* register of device 0.0 to become != 0xffffffff. The PCMCIA
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* PC Card Host System Specification says that when powering
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* up the card, the PCI Spec v2.1 must be followed. In PCI
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* spec v2.2 Table 4-6, Trhfa (Reset High to first Config
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* Access) is at most 2^25 clocks, or just over 1s. Secont
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* 2.2.1 states any card not ready to participate in bus
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* transactions must tristate its outputs. Therefore, any
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* access to its configuration registers must be ignored. In
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* that state, the config reg will read 0xffffffff. Section
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* 6.2.1 states a vendor id of 0xffff is invalid, so this can
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* never match a real card. Print a warning if it never
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* returns a real id. The PCMCIA PC Card Electrical Spec
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* Section 5.2.7.1 implies only device 0.
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*/
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PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL,
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&~CBBM_BRIDGECTRL_RESET, 2);
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@ -966,8 +968,8 @@ cbb_cardbus_reset(device_t brdev, int on)
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count = 1100 / 20;
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do {
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pause("cbbP4", hz * 2 / 100);
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} while (PCIB_READ_CONFIG(brdev, b, 0, 0, PCIR_DEVVENDOR, 2) ==
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0xfffful && --count >= 0);
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} while (PCIB_READ_CONFIG(brdev, b, 0, 0, PCIR_DEVVENDOR, 4) ==
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0xfffffffful && --count >= 0);
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if (count < 0)
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device_printf(brdev, "Warning: Bus reset timeout\n");
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}
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