Ensure the caches have the desired configuration (see especially
cheetah_cache_enable()).
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@ -374,6 +374,7 @@ sparc64_init(caddr_t mdp, u_long o1, u_long o2, u_long o3, ofw_vec_t *vec)
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}
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cache_init(pc);
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cache_enable();
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uma_set_align(pc->pc_cache.dc_linesize - 1);
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cpu_block_copy = bcopy;
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@ -386,6 +386,7 @@ cpu_mp_bootstrap(struct pcpu *pc)
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csa = &cpu_start_args;
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if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
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cheetah_init();
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cache_enable();
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pmap_map_tsb();
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/*
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* Flush all non-locked TLB entries possibly left over by the
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