Update the Chelsio driver to the latest bits from Chelsio
Firmware upgraded to 7.1.0 (from 5.0.0). T3C EEPROM and SRAM added; Code to update eeprom/sram fixed. fl_empty and rx_fifo_ovfl counters can be observed via sysctl. Two new cxgbtool commands to get uP logic analyzer info and uP IOQs Synced up with Chelsio's "common code" (as of 03/03/09) Submitted by: Navdeep Parhar at Chelsio Reviewed by: gnn MFC after: 2 weeks
This commit is contained in:
George V. Neville-Neil
parent
d8a293c142
commit
f2d8ff04fe
@ -22,7 +22,7 @@ unless ($success) {
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my $license = <<END;
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/**************************************************************************
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Copyright (c) 2007-2008, Chelsio Inc.
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Copyright (c) 2007-2009, Chelsio Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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@ -1,6 +1,6 @@
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/**************************************************************************
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Copyright (c) 2007-2008, Chelsio Inc.
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Copyright (c) 2007-2009, Chelsio Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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@ -60,7 +60,17 @@ enum {
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enum { edc_none, edc_sr, edc_twinax };
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/* PHY module I2C device address */
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#define MODULE_DEV_ADDR 0xa0
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enum {
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MODULE_DEV_ADDR = 0xa0,
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SFF_DEV_ADDR = 0xa2,
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};
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/* PHY transceiver type */
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enum {
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phy_transtype_unknown = 0,
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phy_transtype_sfp = 3,
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phy_transtype_xfp = 6,
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};
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#define AEL2005_MODDET_IRQ 4
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@ -71,73 +81,7 @@ struct reg_val {
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unsigned short set_bits;
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};
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static int ael2005_i2c_rd(struct cphy *phy, int dev_addr, int word_addr);
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static int get_module_type (struct cphy *phy, int hint)
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{
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int v;
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v = hint ? hint : ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 0);
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if (v < 0)
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return v;
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if (v == 0x3) {
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/* SFP: see SFF-8472 for below */
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v = ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 3);
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if (v < 0)
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return v;
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if (v == 0x1)
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return phy_modtype_twinax;
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if (v == 0x10)
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return phy_modtype_sr;
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if (v == 0x20)
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return phy_modtype_lr;
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if (v == 0x40)
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return phy_modtype_lrm;
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v = ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 6);
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if (v < 0)
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return v;
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if (v != 4)
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return phy_modtype_unknown;
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v = ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 10);
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if (v < 0)
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return v;
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if (v & 0x80) {
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v = ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 0x12);
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if (v < 0)
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return v;
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return v > 10 ? phy_modtype_twinax_long :
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phy_modtype_twinax;
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}
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} else if (v == 0x6) {
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/* XFP: See INF-8077i for details. */
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v = ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 127);
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if (v < 0)
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return v;
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if (v != 1) {
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/* XXX: set page select to table 1 yourself */
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return phy_modtype_unknown;
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}
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v = ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 131);
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if (v < 0)
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return v;
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if (v == 0x10)
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return phy_modtype_lrm;
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if (v == 0x40)
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return phy_modtype_lr;
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if (v == 0x80)
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return phy_modtype_sr;
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}
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return phy_modtype_unknown;
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}
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static int get_module_type(struct cphy *phy);
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static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)
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{
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@ -164,6 +108,110 @@ static void ael100x_txon(struct cphy *phy)
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msleep(30);
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}
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static int ael_i2c_rd(struct cphy *phy, int dev_addr, int word_addr)
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{
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int i, err;
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unsigned int stat, data;
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err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL,
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(dev_addr << 8) | (1 << 8) | word_addr);
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if (err)
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return err;
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for (i = 0; i < 200; i++) {
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msleep(1);
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err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat);
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if (err)
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return err;
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if ((stat & 3) == 1) {
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err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA,
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&data);
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if (err)
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return err;
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return data >> 8;
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}
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}
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CH_WARN(phy->adapter, "PHY %u I2C read of addr %u timed out\n",
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phy->addr, word_addr);
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return -ETIMEDOUT;
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}
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static int ael_i2c_wr(struct cphy *phy, int dev_addr, int word_addr, int data)
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{
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int i, err;
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unsigned int stat;
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err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA, data);
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if (err)
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return err;
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err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL,
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(dev_addr << 8) | word_addr);
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if (err)
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return err;
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for (i = 0; i < 200; i++) {
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msleep(1);
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err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat);
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if (err)
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return err;
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if ((stat & 3) == 1)
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return 0;
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}
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CH_WARN(phy->adapter, "PHY %u I2C Write of addr %u timed out\n",
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phy->addr, word_addr);
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return -ETIMEDOUT;
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}
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static int get_phytrans_type(struct cphy *phy)
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{
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int v;
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v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0);
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if (v < 0)
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return phy_transtype_unknown;
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return v;
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}
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static int ael_laser_down(struct cphy *phy, int enable)
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{
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int v, dev_addr;
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v = get_phytrans_type(phy);
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if (v < 0)
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return v;
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if (v == phy_transtype_sfp) {
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/* Check SFF Soft TX disable is supported */
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v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 93);
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if (v < 0)
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return v;
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v &= 0x40;
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if (!v)
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return v;
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dev_addr = SFF_DEV_ADDR;
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} else if (v == phy_transtype_xfp)
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dev_addr = MODULE_DEV_ADDR;
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else
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return v;
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v = ael_i2c_rd(phy, dev_addr, 110);
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if (v < 0)
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return v;
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if (enable)
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v |= 0x40;
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else
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v &= ~0x40;
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v = ael_i2c_wr(phy, dev_addr, 110, v);
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return v;
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}
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static int ael1002_power_down(struct cphy *phy, int enable)
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{
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int err;
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@ -182,9 +230,9 @@ static int ael1002_get_module_type(struct cphy *phy, int delay_ms)
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if (delay_ms)
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msleep(delay_ms);
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v = ael2005_i2c_rd(phy, MODULE_DEV_ADDR, 0);
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v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0);
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return v == -ETIMEDOUT ? phy_modtype_none : get_module_type(phy, v);
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return v == -ETIMEDOUT ? phy_modtype_none : get_module_type(phy);
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}
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static int ael1002_reset(struct cphy *phy, int wait)
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@ -273,6 +321,7 @@ int t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
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SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE,
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"10GBASE-R");
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ael100x_txon(phy);
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ael_laser_down(phy, 0);
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err = ael1002_get_module_type(phy, 0);
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if (err >= 0)
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@ -283,31 +332,38 @@ int t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
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static int ael1006_reset(struct cphy *phy, int wait)
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{
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u32 gpio_out;
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t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
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/* Hack to reset the phy correctly */
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/* Read out the current value */
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gpio_out = t3_read_reg(phy->adapter, A_T3DBG_GPIO_EN);
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/* Reset the phy */
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gpio_out &= ~F_GPIO6_OUT_VAL;
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t3_write_reg(phy->adapter, A_T3DBG_GPIO_EN, gpio_out);
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msleep(125);
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/* Take the phy out of reset */
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gpio_out |= F_GPIO6_OUT_VAL;
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t3_write_reg(phy->adapter, A_T3DBG_GPIO_EN, gpio_out);
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msleep(125);
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t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
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int err;
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/* Phy loopback work around for ael1006 */
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/* Soft reset phy by toggling loopback */
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msleep(125);
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/* Put phy into local loopback */
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t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 0, 1);
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msleep(125);
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/* Take phy out of local loopback */
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t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 1, 0);
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err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
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if (err)
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return err;
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return 0;
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t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN,
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F_GPIO6_OUT_VAL, 0);
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msleep(125);
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t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN,
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F_GPIO6_OUT_VAL, F_GPIO6_OUT_VAL);
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msleep(125);
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err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
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if (err)
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return err;
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msleep(125);
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err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 1, 1);
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if (err)
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return err;
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msleep(125);
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err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 1, 0);
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return err;
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}
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static int ael1006_power_down(struct cphy *phy, int enable)
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@ -1047,53 +1103,71 @@ static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)
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return err;
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}
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static int ael2005_i2c_rd(struct cphy *phy, int dev_addr, int word_addr)
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{
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int i, err;
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unsigned int stat, data;
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err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL,
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(dev_addr << 8) | (1 << 8) | word_addr);
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if (err)
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return err;
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for (i = 0; i < 5; i++) {
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msleep(1);
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err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat);
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if (err)
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return err;
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if ((stat & 3) == 1) {
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err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA,
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&data);
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if (err)
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return err;
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return data >> 8;
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}
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}
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CH_WARN(phy->adapter, "PHY %u I2C read of addr %u timed out\n",
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phy->addr, word_addr);
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return -ETIMEDOUT;
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}
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static int ael2005_get_module_type(struct cphy *phy, int delay_ms)
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static int get_module_type(struct cphy *phy)
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{
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int v;
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unsigned int stat;
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v = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, &stat);
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if (v)
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return v;
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v = get_phytrans_type(phy);
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if (v == phy_transtype_sfp) {
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/* SFP: see SFF-8472 for below */
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if (stat & (1 << 8)) /* module absent */
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return phy_modtype_none;
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v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 3);
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if (v < 0)
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return v;
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if (delay_ms)
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msleep(delay_ms);
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if (v == 0x1)
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return phy_modtype_twinax;
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if (v == 0x10)
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return phy_modtype_sr;
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if (v == 0x20)
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return phy_modtype_lr;
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if (v == 0x40)
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return phy_modtype_lrm;
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return get_module_type(phy, 0);
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v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 6);
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if (v < 0)
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return v;
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if (v != 4)
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return phy_modtype_unknown;
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v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 10);
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if (v < 0)
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return v;
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if (v & 0x80) {
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v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 0x12);
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if (v < 0)
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return v;
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return v > 10 ? phy_modtype_twinax_long :
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phy_modtype_twinax;
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}
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} else if (v == phy_transtype_xfp) {
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/* XFP: See INF-8077i for details. */
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v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 127);
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if (v < 0)
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return v;
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if (v != 1) {
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/* XXX: set page select to table 1 yourself */
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return phy_modtype_unknown;
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}
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v = ael_i2c_rd(phy, MODULE_DEV_ADDR, 131);
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if (v < 0)
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return v;
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if (v == 0x10)
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return phy_modtype_lrm;
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if (v == 0x40)
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return phy_modtype_lr;
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if (v == 0x80)
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return phy_modtype_sr;
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}
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return phy_modtype_unknown;
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}
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static int ael2005_intr_enable(struct cphy *phy)
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{
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int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0x200);
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@ -1112,6 +1186,24 @@ static int ael2005_intr_clear(struct cphy *phy)
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return err ? err : t3_phy_lasi_intr_clear(phy);
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}
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static int ael2005_get_module_type(struct cphy *phy, int delay_ms)
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{
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int v;
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unsigned int stat;
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v = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, &stat);
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if (v)
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return v;
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if (stat & (1 << 8)) /* module absent */
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return phy_modtype_none;
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if (delay_ms)
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msleep(delay_ms);
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return get_module_type(phy);
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}
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static int ael2005_reset(struct cphy *phy, int wait)
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{
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static struct reg_val regs0[] = {
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@ -1207,7 +1299,13 @@ static int ael2005_intr_handler(struct cphy *phy)
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}
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ret = t3_phy_lasi_intr_handler(phy);
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return ret < 0 ? ret : ret + cause;
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if (ret < 0)
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return ret;
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ret |= cause;
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if (!ret)
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ret |= cphy_cause_link_change;
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return ret;
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}
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#ifdef C99_NOT_SUPPORTED
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@ -1245,6 +1343,7 @@ int t3_ael2005_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
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SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE |
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SUPPORTED_IRQ, "10GBASE-R");
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msleep(125);
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ael_laser_down(phy, 0);
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err = ael2005_get_module_type(phy, 0);
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if (err >= 0)
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@ -1335,7 +1434,7 @@ static int xaui_direct_get_link_status(struct cphy *phy, int *link_ok,
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{
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if (link_ok) {
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unsigned int status;
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||||
status = t3_read_reg(phy->adapter,
|
||||
XGM_REG(A_XGM_SERDES_STAT0, phy->addr)) |
|
||||
t3_read_reg(phy->adapter,
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007-2008, Chelsio Inc.
|
||||
Copyright (c) 2007-2009, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -92,11 +92,21 @@ enum {
|
||||
(((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
|
||||
|
||||
enum {
|
||||
FW_VERSION_MAJOR = 5,
|
||||
FW_VERSION_MINOR = 0,
|
||||
FW_VERSION_MAJOR = 7,
|
||||
FW_VERSION_MINOR = 1,
|
||||
FW_VERSION_MICRO = 0
|
||||
};
|
||||
|
||||
enum {
|
||||
LA_CTRL = 0x80,
|
||||
LA_DATA = 0x84,
|
||||
LA_ENTRIES = 512
|
||||
};
|
||||
|
||||
enum {
|
||||
IOQ_ENTRIES = 7
|
||||
};
|
||||
|
||||
enum {
|
||||
SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
|
||||
SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
|
||||
@ -143,8 +153,6 @@ struct adapter_info {
|
||||
unsigned char nports0; /* # of ports on channel 0 */
|
||||
unsigned char nports1; /* # of ports on channel 1 */
|
||||
unsigned char phy_base_addr; /* MDIO PHY base address */
|
||||
unsigned char mdien:1;
|
||||
unsigned char mdiinv:1;
|
||||
unsigned int gpio_out; /* GPIO output settings */
|
||||
unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */
|
||||
unsigned long caps; /* adapter capabilities */
|
||||
@ -231,6 +239,8 @@ struct mac_stats {
|
||||
|
||||
unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
|
||||
unsigned long num_resets; /* # times reset due to stuck TX */
|
||||
|
||||
unsigned long link_faults; /* # detected link faults */
|
||||
};
|
||||
|
||||
struct tp_mib_stats {
|
||||
@ -345,6 +355,14 @@ struct vpd_params {
|
||||
unsigned short xauicfg[2];
|
||||
};
|
||||
|
||||
struct generic_vpd {
|
||||
u32 offset;
|
||||
u32 len;
|
||||
u8 *data;
|
||||
};
|
||||
|
||||
enum { MAX_VPD_BYTES = 32000 };
|
||||
|
||||
struct pci_params {
|
||||
unsigned int vpd_cap_addr;
|
||||
unsigned int pcie_cap_addr;
|
||||
@ -674,6 +692,8 @@ int t3_phy_lasi_intr_handler(struct cphy *phy);
|
||||
void t3_intr_enable(adapter_t *adapter);
|
||||
void t3_intr_disable(adapter_t *adapter);
|
||||
void t3_intr_clear(adapter_t *adapter);
|
||||
void t3_xgm_intr_enable(adapter_t *adapter, int idx);
|
||||
void t3_xgm_intr_disable(adapter_t *adapter, int idx);
|
||||
void t3_port_intr_enable(adapter_t *adapter, int idx);
|
||||
void t3_port_intr_disable(adapter_t *adapter, int idx);
|
||||
void t3_port_intr_clear(adapter_t *adapter, int idx);
|
||||
@ -681,29 +701,34 @@ int t3_slow_intr_handler(adapter_t *adapter);
|
||||
int t3_phy_intr_handler(adapter_t *adapter);
|
||||
|
||||
void t3_link_changed(adapter_t *adapter, int port_id);
|
||||
void t3_link_fault(adapter_t *adapter, int port_id);
|
||||
int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
|
||||
const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
|
||||
int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
|
||||
int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
|
||||
int t3_seeprom_wp(adapter_t *adapter, int enable);
|
||||
int t3_get_vpd_len(adapter_t *adapter, struct generic_vpd *vpd);
|
||||
int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd);
|
||||
int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
|
||||
u32 *data, int byte_oriented);
|
||||
int t3_get_tp_version(adapter_t *adapter, u32 *vers);
|
||||
int t3_check_tpsram_version(adapter_t *adapter, int *must_load);
|
||||
int t3_check_tpsram_version(adapter_t *adapter);
|
||||
int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
|
||||
int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
|
||||
int t3_get_fw_version(adapter_t *adapter, u32 *vers);
|
||||
int t3_check_fw_version(adapter_t *adapter, int *must_load);
|
||||
int t3_check_fw_version(adapter_t *adapter);
|
||||
int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size);
|
||||
int t3_init_hw(adapter_t *adapter, u32 fw_params);
|
||||
void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
|
||||
void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
|
||||
int t3_reset_adapter(adapter_t *adapter);
|
||||
int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
|
||||
int t3_reinit_adapter(adapter_t *adap);
|
||||
void t3_led_ready(adapter_t *adapter);
|
||||
void t3_fatal_err(adapter_t *adapter);
|
||||
void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
|
||||
void t3_enable_filters(adapter_t *adap);
|
||||
void t3_disable_filters(adapter_t *adap);
|
||||
void t3_tp_set_offload_mode(adapter_t *adap, int enable);
|
||||
void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
|
||||
const u16 *rspq);
|
||||
@ -720,6 +745,8 @@ int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
|
||||
|
||||
int t3_mac_reset(struct cmac *mac);
|
||||
void t3b_pcs_reset(struct cmac *mac);
|
||||
void t3_mac_disable_exact_filters(struct cmac *mac);
|
||||
void t3_mac_enable_exact_filters(struct cmac *mac);
|
||||
int t3_mac_enable(struct cmac *mac, int which);
|
||||
int t3_mac_disable(struct cmac *mac, int which);
|
||||
int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
|
||||
@ -750,6 +777,8 @@ void t3_get_cong_cntl_tab(adapter_t *adap,
|
||||
unsigned short incr[NMTUS][NCCTRL_WIN]);
|
||||
void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
|
||||
int filter_index, int invert, int enable);
|
||||
void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp,
|
||||
int filter_index, int *inverted, int *enabled);
|
||||
int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
|
||||
int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg);
|
||||
void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps,
|
||||
@ -759,6 +788,10 @@ void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals,
|
||||
unsigned int start, unsigned int n);
|
||||
#endif
|
||||
|
||||
int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index,
|
||||
u32 *size, void *data);
|
||||
int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data);
|
||||
|
||||
void t3_sge_prep(adapter_t *adap, struct sge_params *p);
|
||||
void t3_sge_init(adapter_t *adap, struct sge_params *p);
|
||||
int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
|
||||
@ -795,6 +828,11 @@ int t3_vsc7323_enable(adapter_t *adap, int port, int which);
|
||||
int t3_vsc7323_disable(adapter_t *adap, int port, int which);
|
||||
const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
|
||||
|
||||
int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr,
|
||||
unsigned int *valp);
|
||||
int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr,
|
||||
unsigned int val);
|
||||
|
||||
int t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
||||
const struct mdio_ops *mdio_ops);
|
||||
int t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
Copyright (c) 2007-2009 Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -273,6 +273,14 @@ struct work_request_hdr {
|
||||
#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH)
|
||||
#define F_WR_FLUSH V_WR_FLUSH(1U)
|
||||
|
||||
#define S_WR_CHN 18
|
||||
#define V_WR_CHN(x) ((x) << S_WR_CHN)
|
||||
#define F_WR_CHN V_WR_CHN(1U)
|
||||
|
||||
#define S_WR_CHN_VLD 19
|
||||
#define V_WR_CHN_VLD(x) ((x) << S_WR_CHN_VLD)
|
||||
#define F_WR_CHN_VLD V_WR_CHN_VLD(1U)
|
||||
|
||||
#define S_WR_DATATYPE 20
|
||||
#define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
|
||||
#define F_WR_DATATYPE V_WR_DATATYPE(1U)
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007-2008, Chelsio Inc.
|
||||
Copyright (c) 2007-2009, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -194,21 +194,18 @@ int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
|
||||
static void mi1_init(adapter_t *adap, const struct adapter_info *ai)
|
||||
{
|
||||
u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;
|
||||
u32 val = F_PREEN | V_MDIINV(ai->mdiinv) | V_MDIEN(ai->mdien) |
|
||||
V_CLKDIV(clkdiv);
|
||||
u32 val = F_PREEN | V_CLKDIV(clkdiv);
|
||||
|
||||
if (!(ai->caps & SUPPORTED_10000baseT_Full))
|
||||
val |= V_ST(1);
|
||||
t3_write_reg(adap, A_MI1_CFG, val);
|
||||
}
|
||||
|
||||
#define MDIO_ATTEMPTS 20
|
||||
|
||||
/*
|
||||
* MI1 read/write operations for direct-addressed PHYs.
|
||||
* MI1 read/write operations for clause 22 PHYs.
|
||||
*/
|
||||
static int mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int *valp)
|
||||
int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int *valp)
|
||||
{
|
||||
int ret;
|
||||
u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
|
||||
@ -217,6 +214,7 @@ static int mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
return -EINVAL;
|
||||
|
||||
MDIO_LOCK(adapter);
|
||||
t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
|
||||
t3_write_reg(adapter, A_MI1_ADDR, addr);
|
||||
t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
|
||||
ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
|
||||
@ -226,8 +224,8 @@ static int mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int val)
|
||||
int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int val)
|
||||
{
|
||||
int ret;
|
||||
u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
|
||||
@ -236,6 +234,7 @@ static int mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
return -EINVAL;
|
||||
|
||||
MDIO_LOCK(adapter);
|
||||
t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
|
||||
t3_write_reg(adapter, A_MI1_ADDR, addr);
|
||||
t3_write_reg(adapter, A_MI1_DATA, val);
|
||||
t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
|
||||
@ -245,12 +244,12 @@ static int mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
}
|
||||
|
||||
static struct mdio_ops mi1_mdio_ops = {
|
||||
mi1_read,
|
||||
mi1_write
|
||||
t3_mi1_read,
|
||||
t3_mi1_write
|
||||
};
|
||||
|
||||
/*
|
||||
* MI1 read/write operations for indirect-addressed PHYs.
|
||||
* MI1 read/write operations for clause 45 PHYs.
|
||||
*/
|
||||
static int mi1_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
int reg_addr, unsigned int *valp)
|
||||
@ -259,6 +258,7 @@ static int mi1_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);
|
||||
|
||||
MDIO_LOCK(adapter);
|
||||
t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0);
|
||||
t3_write_reg(adapter, A_MI1_ADDR, addr);
|
||||
t3_write_reg(adapter, A_MI1_DATA, reg_addr);
|
||||
t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
|
||||
@ -281,6 +281,7 @@ static int mi1_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
|
||||
u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);
|
||||
|
||||
MDIO_LOCK(adapter);
|
||||
t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0);
|
||||
t3_write_reg(adapter, A_MI1_ADDR, addr);
|
||||
t3_write_reg(adapter, A_MI1_DATA, reg_addr);
|
||||
t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
|
||||
@ -485,32 +486,32 @@ int t3_phy_lasi_intr_handler(struct cphy *phy)
|
||||
}
|
||||
|
||||
static struct adapter_info t3_adap_info[] = {
|
||||
{ 1, 1, 0, 0, 0,
|
||||
{ 1, 1, 0,
|
||||
F_GPIO2_OEN | F_GPIO4_OEN |
|
||||
F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
|
||||
&mi1_mdio_ops, "Chelsio PE9000" },
|
||||
{ 1, 1, 0, 0, 0,
|
||||
{ 1, 1, 0,
|
||||
F_GPIO2_OEN | F_GPIO4_OEN |
|
||||
F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
|
||||
&mi1_mdio_ops, "Chelsio T302" },
|
||||
{ 1, 0, 0, 0, 0,
|
||||
{ 1, 0, 0,
|
||||
F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
|
||||
F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
|
||||
{ 0 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
|
||||
&mi1_mdio_ext_ops, "Chelsio T310" },
|
||||
{ 1, 1, 0, 0, 0,
|
||||
{ 1, 1, 0,
|
||||
F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
|
||||
F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
|
||||
F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
|
||||
{ S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
|
||||
&mi1_mdio_ext_ops, "Chelsio T320" },
|
||||
{ 4, 0, 0, 0, 0,
|
||||
{ 4, 0, 0,
|
||||
F_GPIO5_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO5_OUT_VAL |
|
||||
F_GPIO6_OUT_VAL | F_GPIO7_OUT_VAL,
|
||||
{ S_GPIO1, S_GPIO2, S_GPIO3, S_GPIO4 }, SUPPORTED_AUI,
|
||||
&mi1_mdio_ops, "Chelsio T304" },
|
||||
{ 0 },
|
||||
{ 1, 0, 0, 0, 0,
|
||||
{ 1, 0, 0,
|
||||
F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO6_OEN | F_GPIO7_OEN |
|
||||
F_GPIO10_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
|
||||
{ S_GPIO9 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
|
||||
@ -747,16 +748,17 @@ enum {
|
||||
SF_ERASE_SECTOR = 0xd8, /* erase sector */
|
||||
|
||||
FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */
|
||||
OLD_FW_VERS_ADDR = 0x77ffc, /* flash address holding FW version */
|
||||
FW_VERS_ADDR = 0x7fffc, /* flash address holding FW version */
|
||||
FW_VERS_ADDR_PRE8 = 0x77ffc,/* flash address holding FW version pre8 */
|
||||
FW_MIN_SIZE = 8, /* at least version and csum */
|
||||
FW_MAX_SIZE = FW_VERS_ADDR - FW_FLASH_BOOT_ADDR,
|
||||
FW_MAX_SIZE_PRE8 = FW_VERS_ADDR_PRE8 - FW_FLASH_BOOT_ADDR,
|
||||
|
||||
BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
|
||||
BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */
|
||||
BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */
|
||||
BOOT_MIN_SIZE = sizeof(boot_header_t), /* at least basic header */
|
||||
BOOT_MAX_SIZE = 0xff*BOOT_SIZE_INC /* 1 byte * length increment */
|
||||
BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC /* 1 byte * length increment */
|
||||
};
|
||||
|
||||
/**
|
||||
@ -885,7 +887,7 @@ int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
|
||||
* at the given address.
|
||||
* If @byte_oriented is set the write data is stored as a 32-bit
|
||||
* big-endian array, otherwise in the processor's native endianess.
|
||||
*
|
||||
*
|
||||
*/
|
||||
static int t3_write_flash(adapter_t *adapter, unsigned int addr,
|
||||
unsigned int n, const u8 *data,
|
||||
@ -946,7 +948,7 @@ int t3_get_tp_version(adapter_t *adapter, u32 *vers)
|
||||
1, 1, 5, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
||||
*vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
|
||||
|
||||
return 0;
|
||||
@ -957,7 +959,7 @@ int t3_get_tp_version(adapter_t *adapter, u32 *vers)
|
||||
* @adapter: the adapter
|
||||
*
|
||||
*/
|
||||
int t3_check_tpsram_version(adapter_t *adapter, int *must_load)
|
||||
int t3_check_tpsram_version(adapter_t *adapter)
|
||||
{
|
||||
int ret;
|
||||
u32 vers;
|
||||
@ -966,26 +968,19 @@ int t3_check_tpsram_version(adapter_t *adapter, int *must_load)
|
||||
if (adapter->params.rev == T3_REV_A)
|
||||
return 0;
|
||||
|
||||
*must_load = 1;
|
||||
|
||||
ret = t3_get_tp_version(adapter, &vers);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
||||
vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
|
||||
|
||||
major = G_TP_VERSION_MAJOR(vers);
|
||||
minor = G_TP_VERSION_MINOR(vers);
|
||||
|
||||
if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
|
||||
if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
|
||||
return 0;
|
||||
|
||||
if (major != TP_VERSION_MAJOR)
|
||||
CH_ERR(adapter, "found wrong TP version (%u.%u), "
|
||||
"driver needs version %d.%d\n", major, minor,
|
||||
TP_VERSION_MAJOR, TP_VERSION_MINOR);
|
||||
else {
|
||||
*must_load = 0;
|
||||
CH_ERR(adapter, "found wrong TP version (%u.%u), "
|
||||
"driver compiled for version %d.%d\n", major, minor,
|
||||
TP_VERSION_MAJOR, TP_VERSION_MINOR);
|
||||
@ -994,7 +989,7 @@ int t3_check_tpsram_version(adapter_t *adapter, int *must_load)
|
||||
}
|
||||
|
||||
/**
|
||||
* t3_check_tpsram - check if provided protocol SRAM
|
||||
* t3_check_tpsram - check if provided protocol SRAM
|
||||
* is compatible with this driver
|
||||
* @adapter: the adapter
|
||||
* @tp_sram: the firmware image to write
|
||||
@ -1031,16 +1026,17 @@ enum fw_version_type {
|
||||
* @adapter: the adapter
|
||||
* @vers: where to place the version
|
||||
*
|
||||
* Reads the FW version from flash.
|
||||
* Reads the FW version from flash. Note that we had to move the version
|
||||
* due to FW size. If we don't find a valid FW version in the new location
|
||||
* we fall back and read the old location.
|
||||
*/
|
||||
int t3_get_fw_version(adapter_t *adapter, u32 *vers)
|
||||
{
|
||||
int ret = t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0);
|
||||
|
||||
if (!ret && *vers != 0xffffffff)
|
||||
return 0;
|
||||
else
|
||||
return t3_read_flash(adapter, OLD_FW_VERS_ADDR, 1, vers, 0);
|
||||
return t3_read_flash(adapter, FW_VERS_ADDR_PRE8, 1, vers, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1050,13 +1046,12 @@ int t3_get_fw_version(adapter_t *adapter, u32 *vers)
|
||||
* Checks if an adapter's FW is compatible with the driver. Returns 0
|
||||
* if the versions are compatible, a negative error otherwise.
|
||||
*/
|
||||
int t3_check_fw_version(adapter_t *adapter, int *must_load)
|
||||
int t3_check_fw_version(adapter_t *adapter)
|
||||
{
|
||||
int ret;
|
||||
u32 vers;
|
||||
unsigned int type, major, minor;
|
||||
|
||||
*must_load = 1;
|
||||
ret = t3_get_fw_version(adapter, &vers);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -1069,16 +1064,11 @@ int t3_check_fw_version(adapter_t *adapter, int *must_load)
|
||||
minor == FW_VERSION_MINOR)
|
||||
return 0;
|
||||
|
||||
if (major != FW_VERSION_MAJOR)
|
||||
CH_ERR(adapter, "found wrong FW version(%u.%u), "
|
||||
"driver needs version %u.%u\n", major, minor,
|
||||
FW_VERSION_MAJOR, FW_VERSION_MINOR);
|
||||
else if ((int)minor < FW_VERSION_MINOR) {
|
||||
*must_load = 0;
|
||||
else if (major != FW_VERSION_MAJOR || minor < FW_VERSION_MINOR)
|
||||
CH_WARN(adapter, "found old FW minor version(%u.%u), "
|
||||
"driver compiled for version %u.%u\n", major, minor,
|
||||
FW_VERSION_MAJOR, FW_VERSION_MINOR);
|
||||
} else {
|
||||
else {
|
||||
CH_WARN(adapter, "found newer FW version(%u.%u), "
|
||||
"driver compiled for version %u.%u\n", major, minor,
|
||||
FW_VERSION_MAJOR, FW_VERSION_MINOR);
|
||||
@ -1123,7 +1113,7 @@ static int t3_flash_erase_sectors(adapter_t *adapter, int start, int end)
|
||||
*/
|
||||
int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size)
|
||||
{
|
||||
u32 csum;
|
||||
u32 version, csum, fw_version_addr;
|
||||
unsigned int i;
|
||||
const u32 *p = (const u32 *)fw_data;
|
||||
int ret, addr, fw_sector = FW_FLASH_BOOT_ADDR >> 16;
|
||||
@ -1133,6 +1123,16 @@ int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size)
|
||||
if (size - 8 > FW_MAX_SIZE)
|
||||
return -EFBIG;
|
||||
|
||||
version = ntohl(*(const u32 *)(fw_data + size - 8));
|
||||
if (G_FW_VERSION_MAJOR(version) < 8) {
|
||||
|
||||
fw_version_addr = FW_VERS_ADDR_PRE8;
|
||||
|
||||
if (size - 8 > FW_MAX_SIZE_PRE8)
|
||||
return -EFBIG;
|
||||
} else
|
||||
fw_version_addr = FW_VERS_ADDR;
|
||||
|
||||
for (csum = 0, i = 0; i < size / sizeof(csum); i++)
|
||||
csum += ntohl(p[i]);
|
||||
if (csum != 0xffffffff) {
|
||||
@ -1158,7 +1158,7 @@ int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size)
|
||||
size -= chunk_size;
|
||||
}
|
||||
|
||||
ret = t3_write_flash(adapter, FW_VERS_ADDR, 4, fw_data, 1);
|
||||
ret = t3_write_flash(adapter, fw_version_addr, 4, fw_data, 1);
|
||||
out:
|
||||
if (ret)
|
||||
CH_ERR(adapter, "firmware download failed, error %d\n", ret);
|
||||
@ -1252,6 +1252,39 @@ int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void t3_gate_rx_traffic(struct cmac *mac, u32 *rx_cfg,
|
||||
u32 *rx_hash_high, u32 *rx_hash_low)
|
||||
{
|
||||
/* stop Rx unicast traffic */
|
||||
t3_mac_disable_exact_filters(mac);
|
||||
|
||||
/* stop broadcast, multicast, promiscuous mode traffic */
|
||||
*rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG);
|
||||
t3_set_reg_field(mac->adapter, A_XGM_RX_CFG,
|
||||
F_ENHASHMCAST | F_DISBCAST | F_COPYALLFRAMES,
|
||||
F_DISBCAST);
|
||||
|
||||
*rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH);
|
||||
t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, 0);
|
||||
|
||||
*rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW);
|
||||
t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, 0);
|
||||
|
||||
/* Leave time to drain max RX fifo */
|
||||
msleep(1);
|
||||
}
|
||||
|
||||
static void t3_open_rx_traffic(struct cmac *mac, u32 rx_cfg,
|
||||
u32 rx_hash_high, u32 rx_hash_low)
|
||||
{
|
||||
t3_mac_enable_exact_filters(mac);
|
||||
t3_set_reg_field(mac->adapter, A_XGM_RX_CFG,
|
||||
F_ENHASHMCAST | F_DISBCAST | F_COPYALLFRAMES,
|
||||
rx_cfg);
|
||||
t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH, rx_hash_high);
|
||||
t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW, rx_hash_low);
|
||||
}
|
||||
|
||||
/**
|
||||
* t3_link_changed - handle interface link changes
|
||||
* @adapter: the adapter
|
||||
@ -1268,9 +1301,32 @@ void t3_link_changed(adapter_t *adapter, int port_id)
|
||||
struct cphy *phy = &pi->phy;
|
||||
struct cmac *mac = &pi->mac;
|
||||
struct link_config *lc = &pi->link_config;
|
||||
int force_link_down = 0;
|
||||
|
||||
phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
|
||||
|
||||
if (!lc->link_ok && link_ok && adapter->params.nports <= 2) {
|
||||
u32 rx_cfg, rx_hash_high, rx_hash_low;
|
||||
u32 status;
|
||||
|
||||
t3_xgm_intr_enable(adapter, port_id);
|
||||
t3_gate_rx_traffic(mac, &rx_cfg, &rx_hash_high, &rx_hash_low);
|
||||
t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0);
|
||||
t3_mac_enable(mac, MAC_DIRECTION_RX);
|
||||
|
||||
status = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset);
|
||||
if (status & F_LINKFAULTCHANGE) {
|
||||
mac->stats.link_faults++;
|
||||
force_link_down = 1;
|
||||
}
|
||||
t3_open_rx_traffic(mac, rx_cfg, rx_hash_high, rx_hash_low);
|
||||
|
||||
if (force_link_down) {
|
||||
t3_os_link_fault_handler(adapter, port_id);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if (lc->requested_fc & PAUSE_AUTONEG)
|
||||
fc &= lc->requested_fc;
|
||||
else
|
||||
@ -1300,6 +1356,57 @@ void t3_link_changed(adapter_t *adapter, int port_id)
|
||||
t3_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc);
|
||||
}
|
||||
|
||||
void t3_link_fault(adapter_t *adapter, int port_id)
|
||||
{
|
||||
struct port_info *pi = adap2pinfo(adapter, port_id);
|
||||
struct cmac *mac = &pi->mac;
|
||||
struct cphy *phy = &pi->phy;
|
||||
struct link_config *lc = &pi->link_config;
|
||||
int link_ok, speed, duplex, fc, link_fault;
|
||||
u32 rx_cfg, rx_hash_high, rx_hash_low;
|
||||
|
||||
if (!pi->link_fault)
|
||||
return; /* nothing to do */
|
||||
|
||||
t3_gate_rx_traffic(mac, &rx_cfg, &rx_hash_high, &rx_hash_low);
|
||||
|
||||
if (adapter->params.rev > 0 && uses_xaui(adapter))
|
||||
t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, 0);
|
||||
|
||||
t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0);
|
||||
t3_mac_enable(mac, MAC_DIRECTION_RX);
|
||||
|
||||
t3_open_rx_traffic(mac, rx_cfg, rx_hash_high, rx_hash_low);
|
||||
|
||||
link_fault = t3_read_reg(adapter,
|
||||
A_XGM_INT_STATUS + mac->offset);
|
||||
link_fault &= F_LINKFAULTCHANGE;
|
||||
|
||||
phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
|
||||
|
||||
if (link_fault) {
|
||||
lc->link_ok = 0;
|
||||
lc->speed = SPEED_INVALID;
|
||||
lc->duplex = DUPLEX_INVALID;
|
||||
|
||||
t3_os_link_fault(adapter, port_id, 0);
|
||||
|
||||
/* Account link faults only when the phy reports a link up */
|
||||
if (link_ok)
|
||||
mac->stats.link_faults++;
|
||||
} else {
|
||||
if (link_ok)
|
||||
t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
|
||||
F_TXACTENABLE | F_RXEN);
|
||||
|
||||
pi->link_fault = 0;
|
||||
lc->link_ok = (unsigned char)link_ok;
|
||||
lc->speed = speed < 0 ? SPEED_INVALID : speed;
|
||||
lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
|
||||
t3_os_link_fault(adapter, port_id, link_ok);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* t3_link_start - apply link configuration to MAC/PHY
|
||||
* @phy: the PHY to setup
|
||||
@ -1335,6 +1442,9 @@ int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
|
||||
fc);
|
||||
/* Also disables autoneg */
|
||||
phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
|
||||
/* PR 5666. Power phy up when doing an ifup */
|
||||
if (!is_10G(phy->adapter))
|
||||
phy->ops->power_down(phy, 0);
|
||||
} else
|
||||
phy->ops->autoneg_enable(phy);
|
||||
} else {
|
||||
@ -1420,7 +1530,7 @@ static int t3_handle_intr_status(adapter_t *adapter, unsigned int reg,
|
||||
#define MC7_INTR_MASK (F_AE | F_UE | F_CE | V_PE(M_PE))
|
||||
#define XGM_INTR_MASK (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \
|
||||
V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR) | \
|
||||
F_TXFIFO_UNDERRUN | F_RXFIFO_OVERFLOW)
|
||||
F_TXFIFO_UNDERRUN)
|
||||
#define PCIX_INTR_MASK (F_MSTDETPARERR | F_SIGTARABT | F_RCVTARABT | \
|
||||
F_RCVMSTABT | F_SIGSYSERR | F_DETPARERR | \
|
||||
F_SPLCMPDIS | F_UNXSPLCMP | F_RCVSPLCMPERR | \
|
||||
@ -1457,11 +1567,11 @@ static int t3_handle_intr_status(adapter_t *adapter, unsigned int reg,
|
||||
V_TX1TPPARERRENB(M_TX1TPPARERRENB) | \
|
||||
V_RXTPPARERRENB(M_RXTPPARERRENB) | \
|
||||
V_MCAPARERRENB(M_MCAPARERRENB))
|
||||
#define XGM_EXTRA_INTR_MASK (F_LINKFAULTCHANGE)
|
||||
#define PL_INTR_MASK (F_T3DBG | F_XGMAC0_0 | F_XGMAC0_1 | F_MC5A | F_PM1_TX | \
|
||||
F_PM1_RX | F_ULP2_TX | F_ULP2_RX | F_TP1 | F_CIM | \
|
||||
F_MC7_CM | F_MC7_PMTX | F_MC7_PMRX | F_SGE3 | F_PCIM0 | \
|
||||
F_MPS0 | F_CPL_SWITCH)
|
||||
|
||||
/*
|
||||
* Interrupt handler for the PCIX1 module.
|
||||
*/
|
||||
@ -1795,7 +1905,15 @@ static int mac_intr_handler(adapter_t *adap, unsigned int idx)
|
||||
|
||||
idx = idx == 0 ? 0 : adapter_info(adap)->nports0; /* MAC idx -> port */
|
||||
mac = &adap2pinfo(adap, idx)->mac;
|
||||
cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset);
|
||||
|
||||
/*
|
||||
* We mask out interrupt causes for which we're not taking interrupts.
|
||||
* This allows us to use polling logic to monitor some of the other
|
||||
* conditions when taking interrupts would impose too much load on the
|
||||
* system.
|
||||
*/
|
||||
cause = (t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset)
|
||||
& ~(F_RXFIFO_OVERFLOW));
|
||||
|
||||
if (cause & V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR)) {
|
||||
mac->stats.tx_fifo_parity_err++;
|
||||
@ -1815,10 +1933,20 @@ static int mac_intr_handler(adapter_t *adap, unsigned int idx)
|
||||
mac->stats.xaui_pcs_ctc_err++;
|
||||
if (cause & F_XAUIPCSALIGNCHANGE)
|
||||
mac->stats.xaui_pcs_align_change++;
|
||||
if (cause & F_XGM_INT) {
|
||||
t3_set_reg_field(adap,
|
||||
A_XGM_INT_ENABLE + mac->offset,
|
||||
F_XGM_INT, 0);
|
||||
mac->stats.link_faults++;
|
||||
|
||||
t3_os_link_fault_handler(adap, idx);
|
||||
}
|
||||
|
||||
t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause);
|
||||
|
||||
if (cause & XGM_INTR_FATAL)
|
||||
t3_fatal_err(adap);
|
||||
|
||||
return cause != 0;
|
||||
}
|
||||
|
||||
@ -1951,9 +2079,7 @@ void t3_intr_enable(adapter_t *adapter)
|
||||
t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0);
|
||||
t3_write_reg(adapter, A_TP_INT_ENABLE,
|
||||
adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff);
|
||||
t3_write_reg(adapter, A_SG_INT_ENABLE,
|
||||
adapter->params.rev >= T3_REV_C ?
|
||||
SGE_INTR_MASK | F_FLEMPTY : SGE_INTR_MASK);
|
||||
t3_write_reg(adapter, A_SG_INT_ENABLE, SGE_INTR_MASK);
|
||||
|
||||
if (adapter->params.rev > 0) {
|
||||
t3_write_reg(adapter, A_CPL_INTR_ENABLE,
|
||||
@ -2031,6 +2157,22 @@ void t3_intr_clear(adapter_t *adapter)
|
||||
(void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
|
||||
}
|
||||
|
||||
void t3_xgm_intr_enable(adapter_t *adapter, int idx)
|
||||
{
|
||||
struct port_info *pi = adap2pinfo(adapter, idx);
|
||||
|
||||
t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset,
|
||||
XGM_EXTRA_INTR_MASK);
|
||||
}
|
||||
|
||||
void t3_xgm_intr_disable(adapter_t *adapter, int idx)
|
||||
{
|
||||
struct port_info *pi = adap2pinfo(adapter, idx);
|
||||
|
||||
t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset,
|
||||
0x7ff);
|
||||
}
|
||||
|
||||
/**
|
||||
* t3_port_intr_enable - enable port-specific interrupts
|
||||
* @adapter: associated adapter
|
||||
@ -2093,23 +2235,54 @@ void t3_port_intr_clear(adapter_t *adapter, int idx)
|
||||
static int t3_sge_write_context(adapter_t *adapter, unsigned int id,
|
||||
unsigned int type)
|
||||
{
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
|
||||
if (type == F_RESPONSEQ) {
|
||||
/*
|
||||
* Can't write the Response Queue Context bits for
|
||||
* Interrupt Armed or the Reserve bits after the chip
|
||||
* has been initialized out of reset. Writing to these
|
||||
* bits can confuse the hardware.
|
||||
*/
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0x17ffffff);
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
|
||||
} else {
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
|
||||
}
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_CMD,
|
||||
V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id));
|
||||
return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
|
||||
0, SG_CONTEXT_CMD_ATTEMPTS, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* clear_sge_ctxt - completely clear an SGE context
|
||||
* @adapter: the adapter
|
||||
* @id: the context id
|
||||
* @type: the context type
|
||||
*
|
||||
* Completely clear an SGE context. Used predominantly at post-reset
|
||||
* initialization. Note in particular that we don't skip writing to any
|
||||
* "sensitive bits" in the contexts the way that t3_sge_write_context()
|
||||
* does ...
|
||||
*/
|
||||
static int clear_sge_ctxt(adapter_t *adap, unsigned int id, unsigned int type)
|
||||
{
|
||||
t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0);
|
||||
t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0);
|
||||
t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0);
|
||||
t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0);
|
||||
return t3_sge_write_context(adap, id, type);
|
||||
t3_write_reg(adap, A_SG_CONTEXT_MASK0, 0xffffffff);
|
||||
t3_write_reg(adap, A_SG_CONTEXT_MASK1, 0xffffffff);
|
||||
t3_write_reg(adap, A_SG_CONTEXT_MASK2, 0xffffffff);
|
||||
t3_write_reg(adap, A_SG_CONTEXT_MASK3, 0xffffffff);
|
||||
t3_write_reg(adap, A_SG_CONTEXT_CMD,
|
||||
V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id));
|
||||
return t3_wait_op_done(adap, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
|
||||
0, SG_CONTEXT_CMD_ATTEMPTS, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -2215,7 +2388,7 @@ int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
|
||||
u64 base_addr, unsigned int size,
|
||||
unsigned int fl_thres, int gen, unsigned int cidx)
|
||||
{
|
||||
unsigned int intr = 0;
|
||||
unsigned int ctrl, intr = 0;
|
||||
|
||||
if (base_addr & 0xfff) /* must be 4K aligned */
|
||||
return -EINVAL;
|
||||
@ -2227,8 +2400,12 @@ int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
|
||||
V_CQ_INDEX(cidx));
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr);
|
||||
base_addr >>= 32;
|
||||
if (irq_vec_idx >= 0)
|
||||
intr = V_RQ_MSI_VEC(irq_vec_idx) | F_RQ_INTR_EN;
|
||||
ctrl = t3_read_reg(adapter, A_SG_CONTROL);
|
||||
if ((irq_vec_idx > 0) ||
|
||||
((irq_vec_idx == 0) && !(ctrl & F_ONEINTMULTQ)))
|
||||
intr = F_RQ_INTR_EN;
|
||||
if (irq_vec_idx >= 0)
|
||||
intr |= V_RQ_MSI_VEC(irq_vec_idx);
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
|
||||
V_CQ_BASE_HI((u32)base_addr) | intr | V_RQ_GEN(gen));
|
||||
t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres);
|
||||
@ -2626,6 +2803,21 @@ void t3_enable_filters(adapter_t *adap)
|
||||
tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, 0, F_LOOKUPEVERYPKT);
|
||||
}
|
||||
|
||||
/**
|
||||
* t3_disable_filters - disable the HW filters
|
||||
* @adap: the adapter
|
||||
*
|
||||
* Disables the HW filters for NIC traffic.
|
||||
*/
|
||||
void t3_disable_filters(adapter_t *adap)
|
||||
{
|
||||
/* note that we don't want to revert to NIC-only mode */
|
||||
t3_set_reg_field(adap, A_MC5_DB_CONFIG, F_FILTEREN, 0);
|
||||
t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG,
|
||||
V_FIVETUPLELOOKUP(M_FIVETUPLELOOKUP), 0);
|
||||
tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, F_LOOKUPEVERYPKT, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* pm_num_pages - calculate the number of pages of the payload memory
|
||||
* @mem_size: the size of the payload memory
|
||||
@ -2719,6 +2911,12 @@ static inline void tp_wr_indirect(adapter_t *adap, unsigned int addr, u32 val)
|
||||
t3_write_reg(adap, A_TP_PIO_DATA, val);
|
||||
}
|
||||
|
||||
static inline u32 tp_rd_indirect(adapter_t *adap, unsigned int addr)
|
||||
{
|
||||
t3_write_reg(adap, A_TP_PIO_ADDR, addr);
|
||||
return t3_read_reg(adap, A_TP_PIO_DATA);
|
||||
}
|
||||
|
||||
static void tp_config(adapter_t *adap, const struct tp_params *p)
|
||||
{
|
||||
t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
|
||||
@ -3130,7 +3328,7 @@ int t3_set_proto_sram(adapter_t *adap, const u8 *data)
|
||||
t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, cpu_to_be32(*buf++));
|
||||
t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++));
|
||||
t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++));
|
||||
|
||||
|
||||
t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
|
||||
if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1))
|
||||
return -EIO;
|
||||
@ -3181,6 +3379,51 @@ void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
|
||||
(void) t3_read_reg(adapter, A_TP_PIO_DATA);
|
||||
}
|
||||
|
||||
/**
|
||||
* t3_query_trace_filter - query a tracing filter
|
||||
* @adapter: the adapter
|
||||
* @tp: the current trace filter parameters
|
||||
* @filter_index: which filter to query
|
||||
* @inverted: non-zero if the filter is inverted
|
||||
* @enabled: non-zero if the filter is enabled
|
||||
*
|
||||
* Returns the current settings of the specified HW tracing filter.
|
||||
*/
|
||||
void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp,
|
||||
int filter_index, int *inverted, int *enabled)
|
||||
{
|
||||
u32 addr, key[4], mask[4];
|
||||
|
||||
addr = filter_index ? A_TP_RX_TRC_KEY0 : A_TP_TX_TRC_KEY0;
|
||||
key[0] = tp_rd_indirect(adapter, addr++);
|
||||
mask[0] = tp_rd_indirect(adapter, addr++);
|
||||
key[1] = tp_rd_indirect(adapter, addr++);
|
||||
mask[1] = tp_rd_indirect(adapter, addr++);
|
||||
key[2] = tp_rd_indirect(adapter, addr++);
|
||||
mask[2] = tp_rd_indirect(adapter, addr++);
|
||||
key[3] = tp_rd_indirect(adapter, addr++);
|
||||
mask[3] = tp_rd_indirect(adapter, addr);
|
||||
|
||||
tp->sport = key[0] & 0xffff;
|
||||
tp->sip = (key[0] >> 16) | ((key[1] & 0xffff) << 16);
|
||||
tp->dport = key[1] >> 16;
|
||||
tp->dip = key[2];
|
||||
tp->proto = key[3] & 0xff;
|
||||
tp->vlan = key[3] >> 8;
|
||||
tp->intf = key[3] >> 20;
|
||||
|
||||
tp->sport_mask = mask[0] & 0xffff;
|
||||
tp->sip_mask = (mask[0] >> 16) | ((mask[1] & 0xffff) << 16);
|
||||
tp->dport_mask = mask[1] >> 16;
|
||||
tp->dip_mask = mask[2];
|
||||
tp->proto_mask = mask[3] & 0xff;
|
||||
tp->vlan_mask = mask[3] >> 8;
|
||||
tp->intf_mask = mask[3] >> 20;
|
||||
|
||||
*inverted = key[3] & (1 << 29);
|
||||
*enabled = key[3] & (1 << 28);
|
||||
}
|
||||
|
||||
/**
|
||||
* t3_config_sched - configure a HW traffic scheduler
|
||||
* @adap: the adapter
|
||||
@ -3615,6 +3858,7 @@ static void config_pcie(adapter_t *adap)
|
||||
|
||||
t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
|
||||
t3_set_reg_field(adap, A_PCIE_CFG, 0,
|
||||
F_ENABLELINKDWNDRST | F_ENABLELINKDOWNRST |
|
||||
F_PCIE_DMASTOPEN | F_PCIE_CLIDECEN);
|
||||
}
|
||||
|
||||
@ -3838,12 +4082,13 @@ void early_hw_init(adapter_t *adapter, const struct adapter_info *ai)
|
||||
{
|
||||
u32 val = V_PORTSPEED(is_10G(adapter) || adapter->params.nports > 2 ?
|
||||
3 : 2);
|
||||
u32 gpio_out = ai->gpio_out;
|
||||
|
||||
mi1_init(adapter, ai);
|
||||
t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */
|
||||
V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1));
|
||||
t3_write_reg(adapter, A_T3DBG_GPIO_EN,
|
||||
ai->gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL);
|
||||
gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL);
|
||||
t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0);
|
||||
t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff));
|
||||
|
||||
@ -3867,9 +4112,9 @@ void early_hw_init(adapter_t *adapter, const struct adapter_info *ai)
|
||||
*
|
||||
* Reset the adapter.
|
||||
*/
|
||||
static int t3_reset_adapter(adapter_t *adapter)
|
||||
int t3_reset_adapter(adapter_t *adapter)
|
||||
{
|
||||
int i, save_and_restore_pcie =
|
||||
int i, save_and_restore_pcie =
|
||||
adapter->params.rev < T3_REV_B2 && is_pcie(adapter);
|
||||
uint16_t devid = 0;
|
||||
|
||||
@ -3947,7 +4192,17 @@ int __devinit t3_prep_adapter(adapter_t *adapter,
|
||||
adapter->params.nports = ai->nports0 + ai->nports1;
|
||||
adapter->params.chan_map = !!ai->nports0 | (!!ai->nports1 << 1);
|
||||
adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
|
||||
adapter->params.linkpoll_period = 0;
|
||||
|
||||
/*
|
||||
* We used to only run the "adapter check task" once a second if
|
||||
* we had PHYs which didn't support interrupts (we would check
|
||||
* their link status once a second). Now we check other conditions
|
||||
* in that routine which would [potentially] impose a very high
|
||||
* interrupt load on the system. As such, we now always scan the
|
||||
* adapter state once a second ...
|
||||
*/
|
||||
adapter->params.linkpoll_period = 10;
|
||||
|
||||
if (adapter->params.nports > 2)
|
||||
adapter->params.stats_update_period = VSC_STATS_ACCUM_SECS;
|
||||
else
|
||||
@ -3995,8 +4250,8 @@ int __devinit t3_prep_adapter(adapter_t *adapter,
|
||||
|
||||
if (is_offload(adapter)) {
|
||||
adapter->params.mc5.nservers = DEFAULT_NSERVERS;
|
||||
adapter->params.mc5.nfilters = adapter->params.rev > 0 ?
|
||||
DEFAULT_NFILTERS : 0;
|
||||
/* PR 6487. TOE and filtering are mutually exclusive */
|
||||
adapter->params.mc5.nfilters = 0;
|
||||
adapter->params.mc5.nroutes = 0;
|
||||
t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT);
|
||||
|
||||
@ -4020,10 +4275,19 @@ int __devinit t3_prep_adapter(adapter_t *adapter,
|
||||
const struct port_type_info *pti;
|
||||
struct port_info *p = adap2pinfo(adapter, i);
|
||||
|
||||
while (!adapter->params.vpd.port_type[j])
|
||||
++j;
|
||||
|
||||
pti = &port_types[adapter->params.vpd.port_type[j]];
|
||||
for (;;) {
|
||||
unsigned port_type = adapter->params.vpd.port_type[j];
|
||||
if (port_type) {
|
||||
if (port_type < ARRAY_SIZE(port_types)) {
|
||||
pti = &port_types[port_type];
|
||||
break;
|
||||
} else
|
||||
return -EINVAL;
|
||||
}
|
||||
j++;
|
||||
if (j >= ARRAY_SIZE(adapter->params.vpd.port_type))
|
||||
return -EINVAL;
|
||||
}
|
||||
ret = pti->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
|
||||
ai->mdio_ops);
|
||||
if (ret)
|
||||
@ -4042,7 +4306,14 @@ int __devinit t3_prep_adapter(adapter_t *adapter,
|
||||
t3_os_set_hw_addr(adapter, i, hw_addr);
|
||||
init_link_config(&p->link_config, p->phy.caps);
|
||||
p->phy.ops->power_down(&p->phy, 1);
|
||||
if (!(p->phy.caps & SUPPORTED_IRQ))
|
||||
|
||||
/*
|
||||
* If the PHY doesn't support interrupts for link status
|
||||
* changes, schedule a scan of the adapter links at least
|
||||
* once a second.
|
||||
*/
|
||||
if (!(p->phy.caps & SUPPORTED_IRQ) &&
|
||||
adapter->params.linkpoll_period > 10)
|
||||
adapter->params.linkpoll_period = 10;
|
||||
}
|
||||
|
||||
@ -4061,7 +4332,7 @@ int __devinit t3_prep_adapter(adapter_t *adapter,
|
||||
int t3_reinit_adapter(adapter_t *adap)
|
||||
{
|
||||
unsigned int i;
|
||||
int ret, j = -1;
|
||||
int ret, j = 0;
|
||||
|
||||
early_hw_init(adap, adap->params.info);
|
||||
ret = init_parity(adap);
|
||||
@ -4076,10 +4347,19 @@ int t3_reinit_adapter(adapter_t *adap)
|
||||
const struct port_type_info *pti;
|
||||
struct port_info *p = adap2pinfo(adap, i);
|
||||
|
||||
while (!adap->params.vpd.port_type[++j])
|
||||
;
|
||||
|
||||
pti = &port_types[adap->params.vpd.port_type[j]];
|
||||
for (;;) {
|
||||
unsigned port_type = adap->params.vpd.port_type[j];
|
||||
if (port_type) {
|
||||
if (port_type < ARRAY_SIZE(port_types)) {
|
||||
pti = &port_types[port_type];
|
||||
break;
|
||||
} else
|
||||
return -EINVAL;
|
||||
}
|
||||
j++;
|
||||
if (j >= ARRAY_SIZE(adap->params.vpd.port_type))
|
||||
return -EINVAL;
|
||||
}
|
||||
ret = pti->phy_prep(&p->phy, adap, p->phy.addr, NULL);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -4114,3 +4394,130 @@ void t3_failover_clear(adapter_t *adapter)
|
||||
t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE,
|
||||
F_PORT0ACTIVE | F_PORT1ACTIVE);
|
||||
}
|
||||
|
||||
static int t3_cim_hac_read(adapter_t *adapter, u32 addr, u32 *val)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
t3_write_reg(adapter, A_CIM_HOST_ACC_CTRL, addr);
|
||||
if (t3_wait_op_done_val(adapter, A_CIM_HOST_ACC_CTRL,
|
||||
F_HOSTBUSY, 0, 10, 10, &v))
|
||||
return -EIO;
|
||||
|
||||
*val = t3_read_reg(adapter, A_CIM_HOST_ACC_DATA);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int t3_cim_hac_write(adapter_t *adapter, u32 addr, u32 val)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, val);
|
||||
|
||||
addr |= F_HOSTWRITE;
|
||||
t3_write_reg(adapter, A_CIM_HOST_ACC_CTRL, addr);
|
||||
|
||||
if (t3_wait_op_done_val(adapter, A_CIM_HOST_ACC_CTRL,
|
||||
F_HOSTBUSY, 0, 10, 5, &v))
|
||||
return -EIO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index,
|
||||
u32 *size, void *data)
|
||||
{
|
||||
u32 v, *buf = data;
|
||||
int i, cnt, ret;
|
||||
|
||||
if (*size < LA_ENTRIES * 4)
|
||||
return -EINVAL;
|
||||
|
||||
ret = t3_cim_hac_read(adapter, LA_CTRL, &v);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
*stopped = !(v & 1);
|
||||
|
||||
/* Freeze LA */
|
||||
if (!*stopped) {
|
||||
ret = t3_cim_hac_write(adapter, LA_CTRL, 0);
|
||||
if (ret)
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < LA_ENTRIES; i++) {
|
||||
v = (i << 2) | (1 << 1);
|
||||
ret = t3_cim_hac_write(adapter, LA_CTRL, v);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
ret = t3_cim_hac_read(adapter, LA_CTRL, &v);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
cnt = 20;
|
||||
while ((v & (1 << 1)) && cnt) {
|
||||
udelay(5);
|
||||
--cnt;
|
||||
ret = t3_cim_hac_read(adapter, LA_CTRL, &v);
|
||||
if (ret)
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (v & (1 << 1))
|
||||
return -EIO;
|
||||
|
||||
ret = t3_cim_hac_read(adapter, LA_DATA, &v);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
*buf++ = v;
|
||||
}
|
||||
|
||||
ret = t3_cim_hac_read(adapter, LA_CTRL, &v);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
*index = (v >> 16) + 4;
|
||||
*size = LA_ENTRIES * 4;
|
||||
out:
|
||||
/* Unfreeze LA */
|
||||
t3_cim_hac_write(adapter, LA_CTRL, 1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data)
|
||||
{
|
||||
u32 v, *buf = data;
|
||||
int i, j, ret;
|
||||
|
||||
if (*size < IOQ_ENTRIES * sizeof(struct t3_ioq_entry))
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
ret = t3_cim_hac_read(adapter, (4 * i), &v);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
*buf++ = v;
|
||||
}
|
||||
|
||||
for (i = 0; i < IOQ_ENTRIES; i++) {
|
||||
u32 base_addr = 0x10 * (i + 1);
|
||||
|
||||
for (j = 0; j < 4; j++) {
|
||||
ret = t3_cim_hac_read(adapter, base_addr + 4 * j, &v);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
*buf++ = v;
|
||||
}
|
||||
}
|
||||
|
||||
*size = IOQ_ENTRIES * sizeof(struct t3_ioq_entry);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
Copyright (c) 2007-2009 Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -186,6 +186,12 @@ static int t3b2_mac_reset(struct cmac *mac)
|
||||
else
|
||||
t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
|
||||
|
||||
/* This will reduce the number of TXTOGGLES */
|
||||
/* Clear: to stop the NIC traffic */
|
||||
t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 0);
|
||||
/* Ensure TX drains */
|
||||
t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN, 0);
|
||||
|
||||
/* PCS in reset */
|
||||
t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
|
||||
(void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
|
||||
@ -239,6 +245,9 @@ static int t3b2_mac_reset(struct cmac *mac)
|
||||
else
|
||||
t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE);
|
||||
|
||||
/* Set: re-enable NIC traffic */
|
||||
t3_set_reg_field(adap, A_MPS_CFG, F_ENFORCEPKT, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -297,7 +306,7 @@ int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void disable_exact_filters(struct cmac *mac)
|
||||
void t3_mac_disable_exact_filters(struct cmac *mac)
|
||||
{
|
||||
unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_LOW_1;
|
||||
|
||||
@ -308,7 +317,7 @@ static void disable_exact_filters(struct cmac *mac)
|
||||
t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */
|
||||
}
|
||||
|
||||
static void enable_exact_filters(struct cmac *mac)
|
||||
void t3_mac_enable_exact_filters(struct cmac *mac)
|
||||
{
|
||||
unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_HIGH_1;
|
||||
|
||||
@ -415,7 +424,7 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
|
||||
|
||||
if (adap->params.rev >= T3_REV_B2 &&
|
||||
(t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
|
||||
disable_exact_filters(mac);
|
||||
t3_mac_disable_exact_filters(mac);
|
||||
v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
|
||||
t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
|
||||
F_ENHASHMCAST | F_COPYALLFRAMES, F_DISBCAST);
|
||||
@ -427,14 +436,14 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
|
||||
if (t3_wait_op_done(adap, reg + mac->offset,
|
||||
F_RXFIFO_EMPTY, 1, 20, 5)) {
|
||||
t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
|
||||
enable_exact_filters(mac);
|
||||
t3_mac_enable_exact_filters(mac);
|
||||
return -EIO;
|
||||
}
|
||||
t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
|
||||
V_RXMAXPKTSIZE(M_RXMAXPKTSIZE),
|
||||
V_RXMAXPKTSIZE(mtu));
|
||||
t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
|
||||
enable_exact_filters(mac);
|
||||
t3_mac_enable_exact_filters(mac);
|
||||
} else
|
||||
t3_set_reg_field(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset,
|
||||
V_RXMAXPKTSIZE(M_RXMAXPKTSIZE),
|
||||
@ -632,28 +641,26 @@ int t3b2_mac_watchdog_task(struct cmac *mac)
|
||||
unsigned int tx_tcnt, tx_xcnt;
|
||||
adapter_t *adap = mac->adapter;
|
||||
struct mac_stats *s = &mac->stats;
|
||||
unsigned int tx_mcnt = (unsigned int)s->tx_frames;
|
||||
u64 tx_mcnt = s->tx_frames;
|
||||
|
||||
if (mac->multiport)
|
||||
tx_mcnt = t3_read_reg(adap, A_XGM_STAT_TX_FRAME_LOW);
|
||||
|
||||
if (mac->multiport) {
|
||||
tx_mcnt = t3_read_reg(adap, A_XGM_STAT_TX_FRAME_LOW);
|
||||
} else {
|
||||
tx_mcnt = (unsigned int)s->tx_frames;
|
||||
}
|
||||
status = 0;
|
||||
tx_xcnt = 1; /* By default tx_xcnt is making progress*/
|
||||
tx_tcnt = mac->tx_tcnt; /* If tx_mcnt is progressing ignore tx_tcnt*/
|
||||
if (tx_mcnt == mac->tx_mcnt && mac->rx_pause == s->rx_pause) {
|
||||
tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
|
||||
A_XGM_TX_SPI4_SOP_EOP_CNT +
|
||||
mac->offset)));
|
||||
A_XGM_TX_SPI4_SOP_EOP_CNT +
|
||||
mac->offset)));
|
||||
if (tx_xcnt == 0) {
|
||||
t3_write_reg(adap, A_TP_PIO_ADDR,
|
||||
A_TP_TX_DROP_CNT_CH0 + macidx(mac));
|
||||
tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
|
||||
A_TP_PIO_DATA)));
|
||||
} else {
|
||||
} else
|
||||
goto out;
|
||||
}
|
||||
|
||||
} else {
|
||||
mac->toggle_cnt = 0;
|
||||
goto out;
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007-2008, Chelsio Inc.
|
||||
Copyright (c) 2007-2009, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -119,9 +119,11 @@ struct port_info {
|
||||
uint8_t txpkt_intf;
|
||||
uint8_t first_qset;
|
||||
uint32_t nqsets;
|
||||
|
||||
int link_fault;
|
||||
|
||||
uint8_t hw_addr[ETHER_ADDR_LEN];
|
||||
struct task timer_reclaim_task;
|
||||
struct task link_fault_task;
|
||||
struct cdev *port_cdev;
|
||||
|
||||
#define PORT_LOCK_NAME_LEN 32
|
||||
@ -214,7 +216,7 @@ struct sge_fl {
|
||||
uint32_t gen;
|
||||
bus_addr_t phys_addr;
|
||||
uint32_t cntxt_id;
|
||||
uint64_t empty;
|
||||
uint32_t empty;
|
||||
bus_dma_tag_t desc_tag;
|
||||
bus_dmamap_t desc_map;
|
||||
bus_dma_tag_t entry_tag;
|
||||
@ -528,6 +530,8 @@ int t3_os_pci_restore_state(struct adapter *adapter);
|
||||
void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status,
|
||||
int speed, int duplex, int fc);
|
||||
void t3_os_phymod_changed(struct adapter *adap, int port_id);
|
||||
void t3_os_link_fault(adapter_t *adapter, int port_id, int state);
|
||||
void t3_os_link_fault_handler(adapter_t *adapter, int port_id);
|
||||
void t3_sge_err_intr_handler(adapter_t *adapter);
|
||||
int t3_offload_tx(struct t3cdev *, struct mbuf *);
|
||||
void t3_os_ext_intr_handler(adapter_t *adapter);
|
||||
|
||||
@ -57,6 +57,8 @@ enum {
|
||||
CH_SET_HW_SCHED,
|
||||
CH_LOAD_BOOT,
|
||||
CH_CLEAR_STATS,
|
||||
CH_GET_UP_LA,
|
||||
CH_GET_UP_IOQS,
|
||||
};
|
||||
|
||||
/* statistics categories */
|
||||
@ -188,6 +190,31 @@ struct ch_eeprom {
|
||||
uint8_t *data;
|
||||
};
|
||||
|
||||
#define LA_BUFSIZE (2 * 1024)
|
||||
struct ch_up_la {
|
||||
uint32_t stopped;
|
||||
uint32_t idx;
|
||||
uint32_t bufsize;
|
||||
uint32_t *data;
|
||||
};
|
||||
|
||||
struct t3_ioq_entry {
|
||||
uint32_t ioq_cp;
|
||||
uint32_t ioq_pp;
|
||||
uint32_t ioq_alen;
|
||||
uint32_t ioq_stats;
|
||||
};
|
||||
|
||||
#define IOQS_BUFSIZE (1024)
|
||||
struct ch_up_ioqs {
|
||||
uint32_t ioq_rx_enable;
|
||||
uint32_t ioq_tx_enable;
|
||||
uint32_t ioq_rx_status;
|
||||
uint32_t ioq_tx_status;
|
||||
uint32_t bufsize;
|
||||
struct t3_ioq_entry *data;
|
||||
};
|
||||
|
||||
#define CHELSIO_SETREG _IOW('f', CH_SETREG, struct ch_reg)
|
||||
#define CHELSIO_GETREG _IOWR('f', CH_GETREG, struct ch_reg)
|
||||
#define CHELSIO_GETMTUTAB _IOR('f', CH_GETMTUTAB, struct ch_mtus)
|
||||
@ -210,4 +237,6 @@ struct ch_eeprom {
|
||||
#define CHELSIO_GET_MIIREG _IOWR('f', CH_GET_MIIREG, struct ch_mii_data)
|
||||
#define CHELSIO_SET_MIIREG _IOW('f', CH_SET_MIIREG, struct ch_mii_data)
|
||||
#define CHELSIO_GET_EEPROM _IOWR('f', CH_GET_EEPROM, struct ch_eeprom)
|
||||
#define CHELSIO_GET_UP_LA _IOWR('f', CH_GET_UP_LA, struct ch_up_la)
|
||||
#define CHELSIO_GET_UP_IOQS _IOWR('f', CH_GET_UP_IOQS, struct ch_up_ioqs)
|
||||
#endif
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007-2008, Chelsio Inc.
|
||||
Copyright (c) 2007-2009, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -115,6 +115,7 @@ static int offload_open(struct port_info *pi);
|
||||
static void touch_bars(device_t dev);
|
||||
static int offload_close(struct t3cdev *tdev);
|
||||
static void cxgb_link_start(struct port_info *p);
|
||||
static void cxgb_link_fault(void *arg, int ncount);
|
||||
|
||||
static device_method_t cxgb_controller_methods[] = {
|
||||
DEVMETHOD(device_probe, cxgb_controller_probe),
|
||||
@ -364,8 +365,8 @@ cxgb_controller_probe(device_t dev)
|
||||
}
|
||||
|
||||
#define FW_FNAME "cxgb_t3fw"
|
||||
#define TPEEPROM_NAME "t3b_tp_eeprom"
|
||||
#define TPSRAM_NAME "t3b_protocol_sram"
|
||||
#define TPEEPROM_NAME "t3%c_tp_eeprom"
|
||||
#define TPSRAM_NAME "t3%c_protocol_sram"
|
||||
|
||||
static int
|
||||
upgrade_fw(adapter_t *sc)
|
||||
@ -403,7 +404,6 @@ cxgb_controller_attach(device_t dev)
|
||||
#ifdef MSI_SUPPORTED
|
||||
int msi_needed, reg;
|
||||
#endif
|
||||
int must_load = 0;
|
||||
char buf[80];
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
@ -553,7 +553,7 @@ cxgb_controller_attach(device_t dev)
|
||||
/* Create a periodic callout for checking adapter status */
|
||||
callout_init(&sc->cxgb_tick_ch, TRUE);
|
||||
|
||||
if ((t3_check_fw_version(sc, &must_load) != 0 && must_load) || force_fw_update) {
|
||||
if (t3_check_fw_version(sc) < 0 || force_fw_update) {
|
||||
/*
|
||||
* Warn user that a firmware update will be attempted in init.
|
||||
*/
|
||||
@ -564,7 +564,7 @@ cxgb_controller_attach(device_t dev)
|
||||
sc->flags |= FW_UPTODATE;
|
||||
}
|
||||
|
||||
if (t3_check_tpsram_version(sc, &must_load) != 0 && must_load) {
|
||||
if (t3_check_tpsram_version(sc) < 0) {
|
||||
/*
|
||||
* Warn user that a firmware update will be attempted in init.
|
||||
*/
|
||||
@ -1019,6 +1019,9 @@ cxgb_port_attach(device_t dev)
|
||||
/* Get the latest mac address, User can use a LAA */
|
||||
bcopy(IF_LLADDR(p->ifp), p->hw_addr, ETHER_ADDR_LEN);
|
||||
t3_sge_init_port(p);
|
||||
|
||||
TASK_INIT(&p->link_fault_task, 0, cxgb_link_fault, p);
|
||||
|
||||
#if defined(LINK_ATTACH)
|
||||
cxgb_link_start(p);
|
||||
t3_link_changed(sc, p->port_id);
|
||||
@ -1139,6 +1142,32 @@ t3_os_pci_restore_state(struct adapter *sc)
|
||||
return (0);
|
||||
}
|
||||
|
||||
void t3_os_link_fault(struct adapter *adap, int port_id, int state)
|
||||
{
|
||||
struct port_info *pi = &adap->port[port_id];
|
||||
|
||||
if (!state) {
|
||||
if_link_state_change(pi->ifp, LINK_STATE_DOWN);
|
||||
return;
|
||||
}
|
||||
|
||||
if (adap->params.nports <= 2) {
|
||||
struct cmac *mac = &pi->mac;
|
||||
|
||||
/* Clear local faults */
|
||||
t3_xgm_intr_disable(adap, port_id);
|
||||
t3_read_reg(adap, A_XGM_INT_STATUS + pi->mac.offset);
|
||||
t3_write_reg(adap, A_XGM_INT_CAUSE + pi->mac.offset, F_XGM_INT);
|
||||
|
||||
t3_set_reg_field(adap, A_XGM_INT_ENABLE + pi->mac.offset,
|
||||
F_XGM_INT, F_XGM_INT);
|
||||
t3_xgm_intr_enable(adap, pi->port_id);
|
||||
t3_mac_enable(mac, MAC_DIRECTION_TX);
|
||||
}
|
||||
|
||||
if_link_state_change(pi->ifp, LINK_STATE_UP);
|
||||
}
|
||||
|
||||
/**
|
||||
* t3_os_link_changed - handle link status changes
|
||||
* @adapter: the adapter associated with the link change
|
||||
@ -1162,17 +1191,41 @@ t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed,
|
||||
if (link_status) {
|
||||
DELAY(10);
|
||||
t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
|
||||
/* Clear errors created by MAC enable */
|
||||
t3_set_reg_field(adapter,
|
||||
A_XGM_STAT_CTRL + pi->mac.offset,
|
||||
F_CLRSTATS, 1);
|
||||
if_link_state_change(pi->ifp, LINK_STATE_UP);
|
||||
/* Clear errors created by MAC enable */
|
||||
t3_set_reg_field(adapter, A_XGM_STAT_CTRL + pi->mac.offset,
|
||||
F_CLRSTATS, 1);
|
||||
|
||||
if (adapter->params.nports <= 2) {
|
||||
/* Clear local faults */
|
||||
t3_xgm_intr_disable(adapter, pi->port_id);
|
||||
t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
|
||||
t3_write_reg(adapter, A_XGM_INT_CAUSE + pi->mac.offset,
|
||||
F_XGM_INT);
|
||||
|
||||
t3_set_reg_field(adapter,
|
||||
A_XGM_INT_ENABLE + pi->mac.offset,
|
||||
F_XGM_INT, F_XGM_INT);
|
||||
t3_xgm_intr_enable(adapter, pi->port_id);
|
||||
}
|
||||
|
||||
if_link_state_change(pi->ifp, LINK_STATE_UP);
|
||||
} else {
|
||||
pi->phy.ops->power_down(&pi->phy, 1);
|
||||
t3_xgm_intr_disable(adapter, pi->port_id);
|
||||
t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
|
||||
if (adapter->params.nports <= 2) {
|
||||
t3_set_reg_field(adapter,
|
||||
A_XGM_INT_ENABLE + pi->mac.offset,
|
||||
F_XGM_INT, 0);
|
||||
}
|
||||
|
||||
/* PR 5666. We shouldn't power down 1G phys */
|
||||
if (is_10G(adapter))
|
||||
pi->phy.ops->power_down(&pi->phy, 1);
|
||||
|
||||
t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
|
||||
t3_mac_disable(mac, MAC_DIRECTION_RX);
|
||||
t3_link_start(&pi->phy, mac, &pi->link_config);
|
||||
t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
|
||||
|
||||
if_link_state_change(pi->ifp, LINK_STATE_DOWN);
|
||||
}
|
||||
}
|
||||
@ -1227,6 +1280,24 @@ t3_os_ext_intr_handler(adapter_t *sc)
|
||||
ADAPTER_UNLOCK(sc);
|
||||
}
|
||||
|
||||
static void
|
||||
cxgb_link_fault(void *arg, int ncount)
|
||||
{
|
||||
struct port_info *pi = arg;
|
||||
|
||||
t3_link_fault(pi->adapter, pi->port_id);
|
||||
}
|
||||
|
||||
void t3_os_link_fault_handler(struct adapter *sc, int port_id)
|
||||
{
|
||||
struct port_info *pi = &sc->port[port_id];
|
||||
|
||||
ADAPTER_LOCK(sc);
|
||||
pi->link_fault = 1;
|
||||
taskqueue_enqueue(sc->tq, &pi->link_fault_task);
|
||||
ADAPTER_UNLOCK(sc);
|
||||
}
|
||||
|
||||
void
|
||||
t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[])
|
||||
{
|
||||
@ -1510,7 +1581,7 @@ update_tpeeprom(struct adapter *adap)
|
||||
uint32_t version;
|
||||
unsigned int major, minor;
|
||||
int ret, len;
|
||||
char rev;
|
||||
char rev, name[32];
|
||||
|
||||
t3_seeprom_read(adap, TP_SRAM_OFFSET, &version);
|
||||
|
||||
@ -1520,8 +1591,9 @@ update_tpeeprom(struct adapter *adap)
|
||||
return;
|
||||
|
||||
rev = t3rev2char(adap);
|
||||
snprintf(name, sizeof(name), TPEEPROM_NAME, rev);
|
||||
|
||||
tpeeprom = firmware_get(TPEEPROM_NAME);
|
||||
tpeeprom = firmware_get(name);
|
||||
if (tpeeprom == NULL) {
|
||||
device_printf(adap->dev, "could not load TP EEPROM: unable to load %s\n",
|
||||
TPEEPROM_NAME);
|
||||
@ -1564,15 +1636,14 @@ update_tpsram(struct adapter *adap)
|
||||
struct firmware *tpsram;
|
||||
#endif
|
||||
int ret;
|
||||
char rev;
|
||||
char rev, name[32];
|
||||
|
||||
rev = t3rev2char(adap);
|
||||
if (!rev)
|
||||
return 0;
|
||||
snprintf(name, sizeof(name), TPSRAM_NAME, rev);
|
||||
|
||||
update_tpeeprom(adap);
|
||||
|
||||
tpsram = firmware_get(TPSRAM_NAME);
|
||||
tpsram = firmware_get(name);
|
||||
if (tpsram == NULL){
|
||||
device_printf(adap->dev, "could not load TP SRAM\n");
|
||||
return (EINVAL);
|
||||
@ -1600,7 +1671,6 @@ update_tpsram(struct adapter *adap)
|
||||
* Called when the first port is enabled, this function performs the
|
||||
* actions necessary to make an adapter operational, such as completing
|
||||
* the initialization of HW modules, and enabling interrupts.
|
||||
*
|
||||
*/
|
||||
static int
|
||||
cxgb_up(struct adapter *sc)
|
||||
@ -1692,7 +1762,7 @@ cxgb_down_locked(struct adapter *sc)
|
||||
|
||||
t3_sge_stop(sc);
|
||||
t3_intr_disable(sc);
|
||||
|
||||
|
||||
if (sc->intr_tag != NULL) {
|
||||
bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag);
|
||||
sc->intr_tag = NULL;
|
||||
@ -2274,6 +2344,7 @@ cxgb_tick_handler(void *arg, int count)
|
||||
adapter_t *sc = (adapter_t *)arg;
|
||||
const struct adapter_params *p = &sc->params;
|
||||
int i;
|
||||
uint32_t cause, reset;
|
||||
|
||||
if(sc->flags & CXGB_SHUTDOWN)
|
||||
return;
|
||||
@ -2282,7 +2353,6 @@ cxgb_tick_handler(void *arg, int count)
|
||||
if (p->linkpoll_period)
|
||||
check_link_status(sc);
|
||||
|
||||
|
||||
sc->check_task_cnt++;
|
||||
|
||||
/*
|
||||
@ -2294,15 +2364,38 @@ cxgb_tick_handler(void *arg, int count)
|
||||
if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map)
|
||||
check_t3b2_mac(sc);
|
||||
|
||||
cause = t3_read_reg(sc, A_SG_INT_CAUSE);
|
||||
reset = 0;
|
||||
if (cause & F_FLEMPTY) {
|
||||
struct sge_qset *qs = &sc->sge.qs[0];
|
||||
|
||||
i = 0;
|
||||
reset |= F_FLEMPTY;
|
||||
|
||||
cause = (t3_read_reg(sc, A_SG_RSPQ_FL_STATUS) >>
|
||||
S_FL0EMPTY) & 0xffff;
|
||||
while (cause) {
|
||||
qs->fl[i].empty += (cause & 1);
|
||||
if (i)
|
||||
qs++;
|
||||
i ^= 1;
|
||||
cause >>= 1;
|
||||
}
|
||||
}
|
||||
t3_write_reg(sc, A_SG_INT_CAUSE, reset);
|
||||
|
||||
for (i = 0; i < sc->params.nports; i++) {
|
||||
struct port_info *pi = &sc->port[i];
|
||||
struct ifnet *ifp = pi->ifp;
|
||||
struct mac_stats *mstats = &pi->mac.stats;
|
||||
struct cmac *mac = &pi->mac;
|
||||
struct mac_stats *mstats = &mac->stats;
|
||||
PORT_LOCK(pi);
|
||||
t3_mac_update_stats(&pi->mac);
|
||||
t3_mac_update_stats(mac);
|
||||
PORT_UNLOCK(pi);
|
||||
|
||||
|
||||
if (pi->link_fault)
|
||||
taskqueue_enqueue(sc->tq, &pi->link_fault_task);
|
||||
|
||||
ifp->if_opackets =
|
||||
mstats->tx_frames_64 +
|
||||
mstats->tx_frames_65_127 +
|
||||
@ -2347,6 +2440,18 @@ cxgb_tick_handler(void *arg, int count)
|
||||
mstats->rx_mac_internal_errs +
|
||||
mstats->rx_short +
|
||||
mstats->rx_fcs_errs;
|
||||
|
||||
if (mac->multiport)
|
||||
continue;
|
||||
|
||||
/* Count rx fifo overflows, once per second */
|
||||
cause = t3_read_reg(sc, A_XGM_INT_CAUSE + mac->offset);
|
||||
reset = 0;
|
||||
if (cause & F_RXFIFO_OVERFLOW) {
|
||||
mac->stats.rx_fifo_ovfl++;
|
||||
reset |= F_RXFIFO_OVERFLOW;
|
||||
}
|
||||
t3_write_reg(sc, A_XGM_INT_CAUSE + mac->offset, reset);
|
||||
}
|
||||
}
|
||||
|
||||
@ -2818,7 +2923,7 @@ cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data,
|
||||
if (regs->len > reglen)
|
||||
regs->len = reglen;
|
||||
else if (regs->len < reglen)
|
||||
error = E2BIG;
|
||||
error = ENOBUFS;
|
||||
|
||||
if (!error) {
|
||||
cxgb_get_regs(sc, regs, buf);
|
||||
@ -2892,6 +2997,53 @@ cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data,
|
||||
PORT_UNLOCK(pi);
|
||||
break;
|
||||
}
|
||||
case CHELSIO_GET_UP_LA: {
|
||||
struct ch_up_la *la = (struct ch_up_la *)data;
|
||||
uint8_t *buf = malloc(LA_BUFSIZE, M_DEVBUF, M_NOWAIT);
|
||||
if (buf == NULL) {
|
||||
return (ENOMEM);
|
||||
}
|
||||
if (la->bufsize < LA_BUFSIZE)
|
||||
error = ENOBUFS;
|
||||
|
||||
if (!error)
|
||||
error = -t3_get_up_la(sc, &la->stopped, &la->idx,
|
||||
&la->bufsize, buf);
|
||||
if (!error)
|
||||
error = copyout(buf, la->data, la->bufsize);
|
||||
|
||||
free(buf, M_DEVBUF);
|
||||
break;
|
||||
}
|
||||
case CHELSIO_GET_UP_IOQS: {
|
||||
struct ch_up_ioqs *ioqs = (struct ch_up_ioqs *)data;
|
||||
uint8_t *buf = malloc(IOQS_BUFSIZE, M_DEVBUF, M_NOWAIT);
|
||||
uint32_t *v;
|
||||
|
||||
if (buf == NULL) {
|
||||
return (ENOMEM);
|
||||
}
|
||||
if (ioqs->bufsize < IOQS_BUFSIZE)
|
||||
error = ENOBUFS;
|
||||
|
||||
if (!error)
|
||||
error = -t3_get_up_ioqs(sc, &ioqs->bufsize, buf);
|
||||
|
||||
if (!error) {
|
||||
v = (uint32_t *)buf;
|
||||
|
||||
ioqs->bufsize -= 4 * sizeof(uint32_t);
|
||||
ioqs->ioq_rx_enable = *v++;
|
||||
ioqs->ioq_tx_enable = *v++;
|
||||
ioqs->ioq_rx_status = *v++;
|
||||
ioqs->ioq_tx_status = *v++;
|
||||
|
||||
error = copyout(v, ioqs->data, ioqs->bufsize);
|
||||
}
|
||||
|
||||
free(buf, M_DEVBUF);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
return (EOPNOTSUPP);
|
||||
break;
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007-2008, Chelsio Inc.
|
||||
Copyright (c) 2007-2009, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -3460,8 +3460,11 @@ t3_add_configured_sysctls(adapter_t *sc)
|
||||
|
||||
for (j = 0; j < pi->nqsets; j++) {
|
||||
struct sge_qset *qs = &sc->sge.qs[pi->first_qset + j];
|
||||
struct sysctl_oid *qspoid, *rspqpoid, *txqpoid, *ctrlqpoid, *lropoid;
|
||||
struct sysctl_oid_list *qspoidlist, *rspqpoidlist, *txqpoidlist, *ctrlqpoidlist, *lropoidlist;
|
||||
struct sysctl_oid *qspoid, *rspqpoid, *txqpoid,
|
||||
*ctrlqpoid, *lropoid;
|
||||
struct sysctl_oid_list *qspoidlist, *rspqpoidlist,
|
||||
*txqpoidlist, *ctrlqpoidlist,
|
||||
*lropoidlist;
|
||||
struct sge_txq *txq = &qs->txq[TXQ_ETH];
|
||||
|
||||
snprintf(qs->namebuf, QS_NAME_LEN, "qs%d", j);
|
||||
@ -3469,7 +3472,14 @@ t3_add_configured_sysctls(adapter_t *sc)
|
||||
qspoid = SYSCTL_ADD_NODE(ctx, poidlist, OID_AUTO,
|
||||
qs->namebuf, CTLFLAG_RD, NULL, "qset statistics");
|
||||
qspoidlist = SYSCTL_CHILDREN(qspoid);
|
||||
|
||||
|
||||
SYSCTL_ADD_UINT(ctx, qspoidlist, OID_AUTO, "fl0_empty",
|
||||
CTLFLAG_RD, &qs->fl[0].empty, 0,
|
||||
"freelist #0 empty");
|
||||
SYSCTL_ADD_UINT(ctx, qspoidlist, OID_AUTO, "fl1_empty",
|
||||
CTLFLAG_RD, &qs->fl[1].empty, 0,
|
||||
"freelist #1 empty");
|
||||
|
||||
rspqpoid = SYSCTL_ADD_NODE(ctx, qspoidlist, OID_AUTO,
|
||||
rspq_name, CTLFLAG_RD, NULL, "rspq statistics");
|
||||
rspqpoidlist = SYSCTL_CHILDREN(rspqpoid);
|
||||
|
||||
@ -13,6 +13,8 @@ __FBSDID("$FreeBSD$");
|
||||
#include <cxgb_t3fw.h>
|
||||
#include <t3b_protocol_sram.h>
|
||||
#include <t3b_tp_eeprom.h>
|
||||
#include <t3c_protocol_sram.h>
|
||||
#include <t3c_tp_eeprom.h>
|
||||
|
||||
static int
|
||||
cxgb_t3fw_modevent(module_t mod, int type, void *unused)
|
||||
@ -80,7 +82,6 @@ DECLARE_MODULE(cxgb_t3b_protocol_sram, cxgb_t3b_protocol_sram_mod, SI_SUB_DRIVER
|
||||
MODULE_VERSION(cxgb_t3b_protocol_sram, 1);
|
||||
MODULE_DEPEND(cxgb_t3b_protocol_sram, firmware, 1, 1, 1);
|
||||
|
||||
|
||||
static int
|
||||
cxgb_t3b_tp_eeprom_modevent(module_t mod, int type, void *unused)
|
||||
{
|
||||
@ -113,3 +114,69 @@ static moduledata_t cxgb_t3b_tp_eeprom_mod = {
|
||||
DECLARE_MODULE(cxgb_t3b_tp_eeprom, cxgb_t3b_tp_eeprom_mod, SI_SUB_DRIVERS, SI_ORDER_FIRST);
|
||||
MODULE_VERSION(cxgb_t3b_tp_eeprom, 1);
|
||||
MODULE_DEPEND(cxgb_t3b_tp_eeprom, firmware, 1, 1, 1);
|
||||
|
||||
static int
|
||||
cxgb_t3c_protocol_sram_modevent(module_t mod, int type, void *unused)
|
||||
{
|
||||
const struct firmware *fp, *parent;
|
||||
int error;
|
||||
switch (type) {
|
||||
case MOD_LOAD:
|
||||
|
||||
fp = firmware_register("cxgb_t3c_protocol_sram", t3c_protocol_sram,
|
||||
(size_t)t3c_protocol_sram_length,
|
||||
0, NULL);
|
||||
if (fp == NULL)
|
||||
goto fail_0;
|
||||
parent = fp;
|
||||
return (0);
|
||||
fail_0:
|
||||
return (ENXIO);
|
||||
case MOD_UNLOAD:
|
||||
error = firmware_unregister("cxgb_t3c_protocol_sram");
|
||||
return (error);
|
||||
}
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
static moduledata_t cxgb_t3c_protocol_sram_mod = {
|
||||
"cxgb_t3c_protocol_sram",
|
||||
cxgb_t3c_protocol_sram_modevent,
|
||||
0
|
||||
};
|
||||
DECLARE_MODULE(cxgb_t3c_protocol_sram, cxgb_t3c_protocol_sram_mod, SI_SUB_DRIVERS, SI_ORDER_FIRST);
|
||||
MODULE_VERSION(cxgb_t3c_protocol_sram, 1);
|
||||
MODULE_DEPEND(cxgb_t3c_protocol_sram, firmware, 1, 1, 1);
|
||||
|
||||
static int
|
||||
cxgb_t3c_tp_eeprom_modevent(module_t mod, int type, void *unused)
|
||||
{
|
||||
const struct firmware *fp, *parent;
|
||||
int error;
|
||||
switch (type) {
|
||||
case MOD_LOAD:
|
||||
|
||||
fp = firmware_register("cxgb_t3c_tp_eeprom", t3c_tp_eeprom,
|
||||
(size_t)t3c_tp_eeprom_length,
|
||||
0, NULL);
|
||||
if (fp == NULL)
|
||||
goto fail_0;
|
||||
parent = fp;
|
||||
return (0);
|
||||
fail_0:
|
||||
return (ENXIO);
|
||||
case MOD_UNLOAD:
|
||||
error = firmware_unregister("cxgb_t3c_tp_eeprom");
|
||||
return (error);
|
||||
}
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
static moduledata_t cxgb_t3c_tp_eeprom_mod = {
|
||||
"cxgb_t3c_tp_eeprom",
|
||||
cxgb_t3c_tp_eeprom_modevent,
|
||||
0
|
||||
};
|
||||
DECLARE_MODULE(cxgb_t3c_tp_eeprom, cxgb_t3c_tp_eeprom_mod, SI_SUB_DRIVERS, SI_ORDER_FIRST);
|
||||
MODULE_VERSION(cxgb_t3c_tp_eeprom, 1);
|
||||
MODULE_DEPEND(cxgb_t3c_tp_eeprom, firmware, 1, 1, 1);
|
||||
|
||||
14124
sys/dev/cxgb/cxgb_t3fw.h
14124
sys/dev/cxgb/cxgb_t3fw.h
File diff suppressed because it is too large
Load Diff
678
sys/dev/cxgb/t3c_protocol_sram.h
Normal file
678
sys/dev/cxgb/t3c_protocol_sram.h
Normal file
@ -0,0 +1,678 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007-2009, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN22
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#define U (unsigned char)
|
||||
|
||||
static unsigned int t3c_protocol_sram_length = 2564;
|
||||
static unsigned char t3c_protocol_sram[2564] = {
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x01, U 0x01, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF3,
|
||||
U 0xD0, U 0x34, U 0x03, U 0xE2,
|
||||
U 0x80, U 0x26, U 0x2A, U 0x41,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF8,
|
||||
U 0x00, U 0x70, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x80,
|
||||
U 0xC6, U 0x04, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xFB,
|
||||
U 0xD0, U 0x34, U 0x03, U 0xE2,
|
||||
U 0x80, U 0x28, U 0x29, U 0x21,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF8,
|
||||
U 0x06, U 0x00, U 0x02, U 0x37,
|
||||
U 0x01, U 0xC5, U 0xC0, U 0x02,
|
||||
U 0x13, U 0x94, U 0x04, U 0x80,
|
||||
U 0xC6, U 0x05, U 0x70, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF8,
|
||||
U 0x82, U 0x00, U 0x02, U 0x06,
|
||||
U 0x37, U 0x03, U 0x08, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x20, U 0x80, U 0x00, U 0x80,
|
||||
U 0x8D, U 0xF4, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF9,
|
||||
U 0xC4, U 0x31, U 0x00, U 0x00,
|
||||
U 0x00, U 0x28, U 0x2C, U 0x81,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x4E, U 0x70, U 0x02, U 0x1D,
|
||||
U 0x00, U 0xC5, U 0xC0, U 0x02,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xC1, U 0x18, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF1,
|
||||
U 0xC0, U 0x00, U 0x03, U 0xE6,
|
||||
U 0x80, U 0x28, U 0x28, U 0x21,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x02,
|
||||
U 0x13, U 0x94, U 0x04, U 0x00,
|
||||
U 0x00, U 0x01, U 0x70, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xFA,
|
||||
U 0x10, U 0x34, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x01, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x60, U 0x00, U 0x00, U 0x06,
|
||||
U 0x20, U 0x03, U 0x08, U 0x02,
|
||||
U 0x70, U 0x00, U 0x00, U 0xF0,
|
||||
U 0x80, U 0x25, U 0x9A, U 0x90,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF9,
|
||||
U 0xC8, U 0x31, U 0x02, U 0x02,
|
||||
U 0x0A, U 0x00, U 0x02, U 0x42,
|
||||
U 0x00, U 0x00, U 0x00, U 0x81,
|
||||
U 0x80, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF1,
|
||||
U 0xC8, U 0x31, U 0x03, U 0xC2,
|
||||
U 0x0A, U 0x96, U 0x2A, U 0x42,
|
||||
U 0x00, U 0x00, U 0x00, U 0x81,
|
||||
U 0x80, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x04, U 0x31, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x04, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF8,
|
||||
U 0x20, U 0xB0, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x13, U 0x94, U 0x04, U 0x00,
|
||||
U 0xC1, U 0x19, U 0x70, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x02,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF8,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x68, U 0x0C, U 0x20, U 0x01,
|
||||
U 0x00, U 0x00, U 0x10, U 0x90,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF9,
|
||||
U 0xC0, U 0x31, U 0xC3, U 0xE6,
|
||||
U 0x00, U 0x26, U 0x6A, U 0x42,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF2,
|
||||
U 0x10, U 0xF4, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x02, U 0x41,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x60, U 0x50, U 0x08, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x02,
|
||||
U 0x70, U 0x0C, U 0x20, U 0xF1,
|
||||
U 0x80, U 0x25, U 0x9A, U 0x90,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF8,
|
||||
U 0x06, U 0x00, U 0x00, U 0x04,
|
||||
U 0x01, U 0x00, U 0x40, U 0x02,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x02,
|
||||
U 0x28, U 0x8C, U 0x10, U 0x80,
|
||||
U 0x85, U 0xC0, U 0x10, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x4E, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF9,
|
||||
U 0xC0, U 0x00, U 0x02, U 0xDA,
|
||||
U 0x00, U 0x06, U 0x1A, U 0x42,
|
||||
U 0x00, U 0x00, U 0x00, U 0x83,
|
||||
U 0x90, U 0x35, U 0xC0, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF9,
|
||||
U 0xCA, U 0x31, U 0xC3, U 0xC6,
|
||||
U 0x0A, U 0x96, U 0x6A, U 0x41,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF8,
|
||||
U 0x4E, U 0x50, U 0x14, U 0x39,
|
||||
U 0x1C, U 0xC5, U 0xC0, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x02,
|
||||
U 0x28, U 0x8C, U 0x10, U 0x80,
|
||||
U 0x85, U 0xC0, U 0x10, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF3,
|
||||
U 0xCA, U 0x33, U 0x23, U 0xD6,
|
||||
U 0x0E, U 0x96, U 0x6A, U 0x41,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF8,
|
||||
U 0x00, U 0x00, U 0x04, U 0x06,
|
||||
U 0x20, U 0xD0, U 0x02, U 0x41,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF8,
|
||||
U 0x00, U 0xD0, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x83,
|
||||
U 0x90, U 0x31, U 0xC0, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xFB,
|
||||
U 0xCA, U 0x33, U 0xE3, U 0xD2,
|
||||
U 0x0E, U 0x96, U 0x6A, U 0x41,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x00, U 0x50, U 0x1A, U 0x10,
|
||||
U 0x00, U 0x30, U 0x02, U 0x41,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x00, U 0x00, U 0x02, U 0x02,
|
||||
U 0x20, U 0x03, U 0x08, U 0x00,
|
||||
U 0x70, U 0x00, U 0x00, U 0xF9,
|
||||
U 0x90, U 0x11, U 0x8A, U 0x90,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF1,
|
||||
U 0xC0, U 0x50, U 0x1B, U 0xA2,
|
||||
U 0x00, U 0xD2, U 0x02, U 0x41,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF8,
|
||||
U 0x40, U 0x00, U 0x02, U 0x03,
|
||||
U 0x00, U 0x10, U 0x00, U 0x02,
|
||||
U 0x70, U 0x00, U 0x00, U 0xE8,
|
||||
U 0x90, U 0x34, U 0x4A, U 0x90,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xFA,
|
||||
U 0x10, U 0xF4, U 0x02, U 0x08,
|
||||
U 0x00, U 0xC0, U 0x02, U 0x41,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x02,
|
||||
U 0x72, U 0x8C, U 0xC8, U 0xD9,
|
||||
U 0x93, U 0x89, U 0x10, U 0x90,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x82, U 0x90, U 0x00, U 0x00,
|
||||
U 0x03, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF2,
|
||||
U 0x00, U 0x00, U 0x03, U 0x20,
|
||||
U 0x00, U 0x26, U 0x12, U 0x41,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF0,
|
||||
U 0x40, U 0x00, U 0x02, U 0x03,
|
||||
U 0x10, U 0x10, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF4,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF9,
|
||||
U 0xD0, U 0x34, U 0x03, U 0xE2,
|
||||
U 0x80, U 0x26, U 0x2A, U 0x41,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0xFF, U 0xFF, U 0xFF, U 0xF2,
|
||||
U 0x08, U 0x34, U 0x02, U 0x30,
|
||||
U 0x00, U 0xC0, U 0x05, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x70, U 0xEA, U 0xA7, U 0x41,
|
||||
};
|
||||
566
sys/dev/cxgb/t3c_tp_eeprom.h
Normal file
566
sys/dev/cxgb/t3c_tp_eeprom.h
Normal file
@ -0,0 +1,566 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007-2009, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN22
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#define U (unsigned char)
|
||||
|
||||
static unsigned int t3c_tp_eeprom_length = 2116;
|
||||
static unsigned char t3c_tp_eeprom[2116] = {
|
||||
U 0x00, U 0x01, U 0x01, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x10,
|
||||
U 0x00, U 0x00, U 0x00, U 0x10,
|
||||
U 0x00, U 0x00, U 0x00, U 0x40,
|
||||
U 0x00, U 0x00, U 0x00, U 0x40,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x41,
|
||||
U 0x2A, U 0x26, U 0x80, U 0xE2,
|
||||
U 0x03, U 0x34, U 0xD0, U 0x03,
|
||||
U 0x00, U 0x40, U 0x60, U 0x0C,
|
||||
U 0x08, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x07, U 0x80,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x21,
|
||||
U 0x29, U 0x28, U 0x80, U 0xE2,
|
||||
U 0x03, U 0x34, U 0xD0, U 0x0B,
|
||||
U 0x00, U 0x57, U 0x60, U 0x0C,
|
||||
U 0x48, U 0x40, U 0x39, U 0x21,
|
||||
U 0x00, U 0x5C, U 0x1C, U 0x70,
|
||||
U 0x23, U 0x00, U 0x60, U 0x80,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x08, U 0x03, U 0x37,
|
||||
U 0x06, U 0x02, U 0x00, U 0x82,
|
||||
U 0x08, U 0x00, U 0x40, U 0xDF,
|
||||
U 0x08, U 0x08, U 0x00, U 0x08,
|
||||
U 0x02, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x81,
|
||||
U 0x2C, U 0x28, U 0x00, U 0x00,
|
||||
U 0x00, U 0x31, U 0xC4, U 0x09,
|
||||
U 0x00, U 0x80, U 0x11, U 0x0C,
|
||||
U 0x00, U 0x00, U 0x00, U 0x20,
|
||||
U 0x00, U 0x5C, U 0x0C, U 0xD0,
|
||||
U 0x21, U 0x00, U 0xE7, U 0x04,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x21,
|
||||
U 0x28, U 0x28, U 0x80, U 0xE6,
|
||||
U 0x03, U 0x00, U 0xC0, U 0x01,
|
||||
U 0x00, U 0x17, U 0x00, U 0x00,
|
||||
U 0x40, U 0x40, U 0x39, U 0x21,
|
||||
U 0x00, U 0x00, U 0x00, U 0x40,
|
||||
U 0x00, U 0x00, U 0x00, U 0x40,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x01, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x34, U 0x10, U 0x0A,
|
||||
U 0xA9, U 0x59, U 0x02, U 0x08,
|
||||
U 0x0F, U 0x00, U 0x00, U 0x27,
|
||||
U 0x80, U 0x30, U 0x00, U 0x62,
|
||||
U 0x00, U 0x00, U 0x00, U 0x06,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x80, U 0x81, U 0x00,
|
||||
U 0x00, U 0x00, U 0x42, U 0x02,
|
||||
U 0x00, U 0x0A, U 0x02, U 0x02,
|
||||
U 0x31, U 0xC8, U 0x09, U 0x00,
|
||||
U 0x00, U 0x00, U 0x18, U 0x08,
|
||||
U 0x00, U 0x00, U 0x20, U 0xA4,
|
||||
U 0x62, U 0xA9, U 0x20, U 0x3C,
|
||||
U 0x10, U 0x83, U 0x1C, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x04, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0x31, U 0x04, U 0x00,
|
||||
U 0x00, U 0x97, U 0x11, U 0x0C,
|
||||
U 0x40, U 0x40, U 0x39, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x40,
|
||||
U 0x00, U 0x00, U 0x0B, U 0x82,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x02, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x90, U 0x10,
|
||||
U 0x00, U 0x00, U 0x01, U 0x20,
|
||||
U 0x0C, U 0x68, U 0x00, U 0x40,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x08, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x20, U 0xA4,
|
||||
U 0x66, U 0x02, U 0x60, U 0x3E,
|
||||
U 0x1C, U 0x03, U 0x9C, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x41,
|
||||
U 0x02, U 0x00, U 0x00, U 0x04,
|
||||
U 0x00, U 0xF4, U 0x10, U 0x02,
|
||||
U 0xA9, U 0x59, U 0x02, U 0x18,
|
||||
U 0x0F, U 0xC2, U 0x00, U 0x27,
|
||||
U 0x00, U 0x00, U 0x00, U 0x40,
|
||||
U 0x80, U 0x00, U 0x05, U 0x06,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x02, U 0x40, U 0x00, U 0x01,
|
||||
U 0x04, U 0x00, U 0x00, U 0x06,
|
||||
U 0x08, U 0x00, U 0x01, U 0x5C,
|
||||
U 0x08, U 0x08, U 0xC1, U 0x88,
|
||||
U 0x22, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x4E, U 0x00,
|
||||
U 0x00, U 0x5C, U 0x03, U 0x39,
|
||||
U 0x08, U 0x00, U 0x00, U 0x20,
|
||||
U 0xA4, U 0x61, U 0x00, U 0xA0,
|
||||
U 0x2D, U 0x00, U 0x00, U 0x9C,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0xA4,
|
||||
U 0x66, U 0xA9, U 0x60, U 0x3C,
|
||||
U 0x1C, U 0xA3, U 0x9C, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0xC0, U 0xC5, U 0x1C, U 0x39,
|
||||
U 0x14, U 0x50, U 0x4E, U 0x08,
|
||||
U 0x00, U 0x01, U 0x5C, U 0x08,
|
||||
U 0x08, U 0xC1, U 0x88, U 0x22,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0xA4,
|
||||
U 0x66, U 0xE9, U 0x60, U 0x3D,
|
||||
U 0x32, U 0xA3, U 0x3C, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x41,
|
||||
U 0x02, U 0xD0, U 0x20, U 0x06,
|
||||
U 0x04, U 0x00, U 0x00, U 0x08,
|
||||
U 0x00, U 0x1C, U 0x03, U 0x39,
|
||||
U 0x08, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x0D, U 0x80,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0xA4,
|
||||
U 0x66, U 0xE9, U 0x20, U 0x3D,
|
||||
U 0x3E, U 0xA3, U 0xBC, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x41,
|
||||
U 0x02, U 0x30, U 0x00, U 0x10,
|
||||
U 0x1A, U 0x50, U 0x00, U 0x00,
|
||||
U 0xA9, U 0x18, U 0x01, U 0x99,
|
||||
U 0x0F, U 0x00, U 0x00, U 0x07,
|
||||
U 0x80, U 0x30, U 0x00, U 0x22,
|
||||
U 0x20, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x41,
|
||||
U 0x02, U 0xD2, U 0x00, U 0xA2,
|
||||
U 0x1B, U 0x50, U 0xC0, U 0x01,
|
||||
U 0xA9, U 0x44, U 0x03, U 0x89,
|
||||
U 0x0E, U 0x00, U 0x00, U 0x27,
|
||||
U 0x00, U 0x00, U 0x01, U 0x30,
|
||||
U 0x20, U 0x00, U 0x00, U 0x84,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x04, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x41,
|
||||
U 0x02, U 0xC0, U 0x00, U 0x08,
|
||||
U 0x02, U 0xF4, U 0x10, U 0x0A,
|
||||
U 0x09, U 0x91, U 0x38, U 0x99,
|
||||
U 0x8D, U 0xCC, U 0x28, U 0x27,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x03,
|
||||
U 0x00, U 0x00, U 0x90, U 0x82,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x10,
|
||||
U 0x00, U 0x00, U 0x00, U 0x10,
|
||||
U 0x24, U 0x61, U 0x02, U 0x00,
|
||||
U 0x32, U 0x00, U 0x00, U 0x20,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x00, U 0x00,
|
||||
U 0x01, U 0x00, U 0x10, U 0x10,
|
||||
U 0x03, U 0x02, U 0x00, U 0x40,
|
||||
U 0x00, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x10, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x40, U 0x00, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x01, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x04, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x10, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x40, U 0x00, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x01, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x04, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x10, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x40, U 0x00,
|
||||
U 0x00, U 0x00, U 0x00, U 0x01,
|
||||
U 0x00, U 0x00, U 0x00, U 0x41,
|
||||
U 0x2A, U 0x26, U 0x80, U 0xE2,
|
||||
U 0x03, U 0x34, U 0xD0, U 0x09,
|
||||
U 0x00, U 0x00, U 0x00, U 0x10,
|
||||
U 0x00, U 0x00, U 0x00, U 0x10,
|
||||
U 0x50, U 0x00, U 0x0C, U 0x00,
|
||||
U 0x23, U 0x40, U 0x83, U 0x20,
|
||||
U 0x65, U 0x4D, U 0x43, U 0x8B,
|
||||
};
|
||||
@ -1,6 +1,6 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007-2008, Chelsio Inc.
|
||||
Copyright (c) 2007-2009, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
@ -92,6 +92,8 @@ static void __attribute__((noreturn)) usage(FILE *fp)
|
||||
"\tclearstats clear MAC statistics\n"
|
||||
"\tcontext <type> <id> show an SGE context\n"
|
||||
"\tdesc <qset> <queue> <idx> [<cnt>] dump SGE descriptors\n"
|
||||
"\tioqs dump uP IOQs\n"
|
||||
"\tla dump uP logic analyzer info\n"
|
||||
"\tloadboot <boot image> download boot image\n"
|
||||
"\tloadfw <FW image> download firmware\n"
|
||||
"\tmdio <phy_addr> <mmd_addr>\n"
|
||||
@ -673,7 +675,7 @@ static void show_fl_cntxt(uint32_t data[])
|
||||
printf("queue size: %u\n", (data[2] >> 4) & 0xffff);
|
||||
printf("generation: %u\n", (data[2] >> 20) & 1);
|
||||
printf("entry size: %u\n",
|
||||
((data[2] >> 21) & 0x7ff) | (data[3] & 0x1fffff));
|
||||
(data[2] >> 21) | (data[3] & 0x1fffff) << 11);
|
||||
printf("congest thr: %u\n", (data[3] >> 21) & 0x3ff);
|
||||
printf("GTS: %u\n", (data[3] >> 31) & 1);
|
||||
}
|
||||
@ -958,7 +960,7 @@ static int dump_mc7(int argc, char *argv[], int start_arg,
|
||||
#endif
|
||||
|
||||
/* Max FW size is 32K including version, +4 bytes for the checksum. */
|
||||
#define MAX_FW_IMAGE_SIZE (32768 + 4)
|
||||
#define MAX_FW_IMAGE_SIZE (64 * 1024)
|
||||
|
||||
static int load_fw(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
{
|
||||
@ -1330,6 +1332,7 @@ static int pktsched(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clear_stats(int argc, char *argv[], int start_arg,
|
||||
const char *iff_name)
|
||||
{
|
||||
@ -1339,6 +1342,72 @@ static int clear_stats(int argc, char *argv[], int start_arg,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_up_la(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
{
|
||||
struct ch_up_la la;
|
||||
int i, idx, max_idx, entries;
|
||||
|
||||
la.stopped = 0;
|
||||
la.idx = -1;
|
||||
la.bufsize = LA_BUFSIZE;
|
||||
la.data = malloc(la.bufsize);
|
||||
if (!la.data)
|
||||
err(1, "uP_LA malloc");
|
||||
|
||||
if (doit(iff_name, CHELSIO_GET_UP_LA, &la) < 0)
|
||||
err(1, "uP_LA");
|
||||
|
||||
if (la.stopped)
|
||||
printf("LA is not running\n");
|
||||
|
||||
entries = la.bufsize / 4;
|
||||
idx = (int)la.idx;
|
||||
max_idx = (entries / 4) - 1;
|
||||
for (i = 0; i < max_idx; i++) {
|
||||
printf("%04x %08x %08x\n",
|
||||
la.data[idx], la.data[idx+2], la.data[idx+1]);
|
||||
idx = (idx + 4) & (entries - 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_up_ioqs(int argc, char *argv[], int start_arg, const char *iff_name)
|
||||
{
|
||||
struct ch_up_ioqs ioqs;
|
||||
int i, entries;
|
||||
|
||||
bzero(&ioqs, sizeof(ioqs));
|
||||
ioqs.bufsize = IOQS_BUFSIZE;
|
||||
ioqs.data = malloc(IOQS_BUFSIZE);
|
||||
if (!ioqs.data)
|
||||
err(1, "uP_IOQs malloc");
|
||||
|
||||
if (doit(iff_name, CHELSIO_GET_UP_IOQS, &ioqs) < 0)
|
||||
err(1, "uP_IOQs");
|
||||
|
||||
printf("ioq_rx_enable : 0x%08x\n", ioqs.ioq_rx_enable);
|
||||
printf("ioq_tx_enable : 0x%08x\n", ioqs.ioq_tx_enable);
|
||||
printf("ioq_rx_status : 0x%08x\n", ioqs.ioq_rx_status);
|
||||
printf("ioq_tx_status : 0x%08x\n", ioqs.ioq_tx_status);
|
||||
|
||||
entries = ioqs.bufsize / sizeof(struct t3_ioq_entry);
|
||||
for (i = 0; i < entries; i++) {
|
||||
printf("\nioq[%d].cp : 0x%08x\n", i,
|
||||
ioqs.data[i].ioq_cp);
|
||||
printf("ioq[%d].pp : 0x%08x\n", i,
|
||||
ioqs.data[i].ioq_pp);
|
||||
printf("ioq[%d].alen : 0x%08x\n", i,
|
||||
ioqs.data[i].ioq_alen);
|
||||
printf("ioq[%d].stats : 0x%08x\n", i,
|
||||
ioqs.data[i].ioq_stats);
|
||||
printf(" sop %u\n", ioqs.data[i].ioq_stats >> 16);
|
||||
printf(" eop %u\n", ioqs.data[i].ioq_stats & 0xFFFF);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int r = -1;
|
||||
@ -1397,6 +1466,10 @@ int main(int argc, char *argv[])
|
||||
r = get_tcb2(argc, argv, 3, iff_name);
|
||||
else if (!strcmp(argv[2], "clearstats"))
|
||||
r = clear_stats(argc, argv, 3, iff_name);
|
||||
else if (!strcmp(argv[2], "la"))
|
||||
r = get_up_la(argc, argv, 3, iff_name);
|
||||
else if (!strcmp(argv[2], "ioqs"))
|
||||
r = get_up_ioqs(argc, argv, 3, iff_name);
|
||||
|
||||
if (r == -1)
|
||||
usage(stderr);
|
||||
|
||||
@ -26,7 +26,7 @@
|
||||
#define __CXGBTOOL_VERSION_H
|
||||
|
||||
#define PROGNAME "cxgbtool"
|
||||
#define VERSION "1.15f"
|
||||
#define COPYRIGHT "Copyright (c) 2004-2008 Chelsio Communications"
|
||||
#define VERSION "1.16f"
|
||||
#define COPYRIGHT "Copyright (c) 2004-2009 Chelsio Communications"
|
||||
|
||||
#endif //__CXGBTOOL_VERSION_H
|
||||
|
||||
Loading…
Reference in New Issue
Block a user