Fix up the EDMA RX setup path to correctly initialise and reset the RX FIFO.
The original code was .. well, slightly more than incorrect. It showed up as stalled RX queues if the NIC needed to be frequently reinitialised (eg during scans.) This is inspired by work done by Matt Dillon over at the DragonflyBSD project. So: * track when EDMA RX has been stopped and when the MAC has been reset; * re-initialise the ring only after a reset; * track whether RX has been stopped/started - just for debugging now; * don't bother with the RX EOL stuff for EDMA - we don't need the interrupt at all. We also don't need to disable/enable the interrupt or start DMA - once new frames are pushed into the ring via the normal RX path, it'll just restart RX DMA on its own. Tested: * AR9380, STA mode * AR9380, AP mode * AR9485, STA mode * AR9462, STA mode
This commit is contained in:
adrian
parent
078619979c
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f3617deb72
@ -1715,12 +1715,22 @@ ath_suspend(struct ath_softc *sc)
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* NB: don't worry about putting the chip in low power
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* mode; pci will power off our socket on suspend and
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* CardBus detaches the device.
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*
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* XXX TODO: well, that's great, except for non-cardbus
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* devices!
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*/
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/*
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* XXX ensure none of the taskqueues are running
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* XXX This doesn't wait until all pending taskqueue
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* items and parallel transmit/receive/other threads
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* are running!
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*/
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ath_hal_intrset(sc->sc_ah, 0);
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taskqueue_block(sc->sc_tq);
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callout_drain(&sc->sc_cal_ch);
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/*
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* XXX ensure sc_invalid is 1
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* XXX ensure the calibration callout is disabled
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*/
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/* Disable the PCIe PHY, complete with workarounds */
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@ -1811,6 +1821,11 @@ ath_resume(struct ath_softc *sc)
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AH_FALSE, &status);
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ath_reset_keycache(sc);
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ATH_RX_LOCK(sc);
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sc->sc_rx_stopped = 1;
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sc->sc_rx_resetted = 1;
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ATH_RX_UNLOCK(sc);
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/* Let DFS at it in case it's a DFS channel */
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ath_dfs_radar_enable(sc, ic->ic_curchan);
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@ -2015,44 +2030,46 @@ ath_intr(void *arg)
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if (status & HAL_INT_RXEOL) {
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int imask;
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ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL");
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ATH_PCU_LOCK(sc);
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if (! sc->sc_isedma) {
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ATH_PCU_LOCK(sc);
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/*
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* NB: the hardware should re-read the link when
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* RXE bit is written, but it doesn't work at
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* least on older hardware revs.
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*/
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sc->sc_stats.ast_rxeol++;
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/*
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* Disable RXEOL/RXORN - prevent an interrupt
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* storm until the PCU logic can be reset.
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* In case the interface is reset some other
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* way before "sc_kickpcu" is called, don't
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* modify sc_imask - that way if it is reset
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* by a call to ath_reset() somehow, the
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* interrupt mask will be correctly reprogrammed.
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*/
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imask = sc->sc_imask;
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imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN);
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ath_hal_intrset(ah, imask);
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/*
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* Only blank sc_rxlink if we've not yet kicked
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* the PCU.
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*
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* This isn't entirely correct - the correct solution
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* would be to have a PCU lock and engage that for
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* the duration of the PCU fiddling; which would include
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* running the RX process. Otherwise we could end up
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* messing up the RX descriptor chain and making the
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* RX desc list much shorter.
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*/
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if (! sc->sc_kickpcu)
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sc->sc_rxlink = NULL;
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sc->sc_kickpcu = 1;
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ATH_PCU_UNLOCK(sc);
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}
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/*
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* NB: the hardware should re-read the link when
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* RXE bit is written, but it doesn't work at
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* least on older hardware revs.
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*/
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sc->sc_stats.ast_rxeol++;
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/*
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* Disable RXEOL/RXORN - prevent an interrupt
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* storm until the PCU logic can be reset.
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* In case the interface is reset some other
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* way before "sc_kickpcu" is called, don't
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* modify sc_imask - that way if it is reset
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* by a call to ath_reset() somehow, the
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* interrupt mask will be correctly reprogrammed.
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*/
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imask = sc->sc_imask;
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imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN);
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ath_hal_intrset(ah, imask);
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/*
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* Only blank sc_rxlink if we've not yet kicked
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* the PCU.
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*
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* This isn't entirely correct - the correct solution
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* would be to have a PCU lock and engage that for
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* the duration of the PCU fiddling; which would include
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* running the RX process. Otherwise we could end up
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* messing up the RX descriptor chain and making the
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* RX desc list much shorter.
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*/
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if (! sc->sc_kickpcu)
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sc->sc_rxlink = NULL;
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sc->sc_kickpcu = 1;
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ATH_PCU_UNLOCK(sc);
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/*
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* Enqueue an RX proc, to handled whatever
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* Enqueue an RX proc to handle whatever
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* is in the RX queue.
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* This will then kick the PCU.
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* This will then kick the PCU if required.
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*/
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sc->sc_rx.recv_sched(sc, 1);
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}
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@ -2348,6 +2365,12 @@ ath_init(void *arg)
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ATH_UNLOCK(sc);
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return;
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}
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ATH_RX_LOCK(sc);
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sc->sc_rx_stopped = 1;
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sc->sc_rx_resetted = 1;
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ATH_RX_UNLOCK(sc);
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ath_chan_change(sc, ic->ic_curchan);
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/* Let DFS at it in case it's a DFS channel */
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@ -2406,8 +2429,7 @@ ath_init(void *arg)
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* Enable interrupts.
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*/
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sc->sc_imask = HAL_INT_RX | HAL_INT_TX
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| HAL_INT_RXEOL | HAL_INT_RXORN
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| HAL_INT_TXURN
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| HAL_INT_RXORN | HAL_INT_TXURN
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| HAL_INT_FATAL | HAL_INT_GLOBAL;
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/*
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@ -2417,6 +2439,14 @@ ath_init(void *arg)
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if (sc->sc_isedma)
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sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP);
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/*
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* If we're an EDMA NIC, we don't care about RXEOL.
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* Writing a new descriptor in will simply restart
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* RX DMA.
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*/
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if (! sc->sc_isedma)
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sc->sc_imask |= HAL_INT_RXEOL;
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/*
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* Enable MIB interrupts when there are hardware phy counters.
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* Note we only do this (at the moment) for station mode.
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@ -2735,6 +2765,11 @@ ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type)
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__func__, status);
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sc->sc_diversity = ath_hal_getdiversity(ah);
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ATH_RX_LOCK(sc);
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sc->sc_rx_stopped = 1;
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sc->sc_rx_resetted = 1;
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ATH_RX_UNLOCK(sc);
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/* Let DFS at it in case it's a DFS channel */
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ath_dfs_radar_enable(sc, ic->ic_curchan);
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@ -5333,14 +5368,15 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
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ATH_PCU_LOCK(sc);
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/* Disable interrupts */
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ath_hal_intrset(ah, 0);
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/* Stop new RX/TX/interrupt completion */
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if (ath_reset_grablock(sc, 1) == 0) {
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device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
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__func__);
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}
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ath_hal_intrset(ah, 0);
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/* Stop pending RX/TX completion */
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ath_txrx_stop_locked(sc);
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@ -5384,6 +5420,11 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
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}
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sc->sc_diversity = ath_hal_getdiversity(ah);
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ATH_RX_LOCK(sc);
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sc->sc_rx_stopped = 1;
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sc->sc_rx_resetted = 1;
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ATH_RX_UNLOCK(sc);
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/* Let DFS at it in case it's a DFS channel */
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ath_dfs_radar_enable(sc, chan);
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@ -160,10 +160,20 @@ ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
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struct ath_hal *ah = sc->sc_ah;
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ATH_RX_LOCK(sc);
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ath_hal_stoppcurecv(ah);
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ath_hal_setrxfilter(ah, 0);
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ath_hal_stopdmarecv(ah);
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/*
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*
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*/
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if (ath_hal_stopdmarecv(ah) == AH_TRUE)
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sc->sc_rx_stopped = 1;
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/*
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* Give the various bus FIFOs (not EDMA descriptor FIFO)
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* time to finish flushing out data.
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*/
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DELAY(3000);
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/* Flush RX pending for each queue */
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@ -218,10 +228,6 @@ ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
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/*
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* Start receive.
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*
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* XXX TODO: this needs to reallocate the FIFO entries when a reset
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* occurs, in case the FIFO is filled up and no new descriptors get
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* thrown into the FIFO.
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*/
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static int
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ath_edma_startrecv(struct ath_softc *sc)
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@ -230,35 +236,31 @@ ath_edma_startrecv(struct ath_softc *sc)
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ATH_RX_LOCK(sc);
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/*
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* Sanity check - are we being called whilst RX
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* isn't stopped? If so, we may end up pushing
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* too many entries into the RX FIFO and
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* badness occurs.
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*/
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/* Enable RX FIFO */
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ath_hal_rxena(ah);
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/*
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* Entries should only be written out if the
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* FIFO is empty.
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*
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* XXX This isn't correct. I should be looking
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* at the value of AR_RXDP_SIZE (0x0070) to determine
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* how many entries are in here.
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*
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* A warm reset will clear the registers but not the FIFO.
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*
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* And I believe this is actually the address of the last
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* handled buffer rather than the current FIFO pointer.
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* So if no frames have been (yet) seen, we'll reinit the
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* FIFO.
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*
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* I'll chase that up at some point.
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* In theory the hardware has been initialised, right?
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*/
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if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_HP) == 0) {
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if (sc->sc_rx_resetted == 1) {
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DPRINTF(sc, ATH_DEBUG_EDMA_RX,
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"%s: Re-initing HP FIFO\n", __func__);
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ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP);
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}
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if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_LP) == 0) {
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DPRINTF(sc, ATH_DEBUG_EDMA_RX,
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"%s: Re-initing LP FIFO\n", __func__);
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ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_LP);
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sc->sc_rx_resetted = 0;
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} else {
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device_printf(sc->sc_dev,
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"%s: called without resetting chip?\n",
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__func__);
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}
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/* Add up to m_fifolen entries in each queue */
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@ -266,6 +268,9 @@ ath_edma_startrecv(struct ath_softc *sc)
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* These must occur after the above write so the FIFO buffers
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* are pushed/tracked in the same order as the hardware will
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* process them.
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*
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* XXX TODO: is this really necessary? We should've stopped
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* the hardware already and reinitialised it, so it's a no-op.
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*/
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ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP,
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sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen);
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@ -276,6 +281,11 @@ ath_edma_startrecv(struct ath_softc *sc)
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ath_mode_init(sc);
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ath_hal_startpcurecv(ah);
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/*
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* We're now doing RX DMA!
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*/
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sc->sc_rx_stopped = 0;
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ATH_RX_UNLOCK(sc);
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return (0);
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@ -380,6 +390,21 @@ ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
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ATH_RX_LOCK(sc);
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#if 1
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if (sc->sc_rx_resetted == 1) {
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/*
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* XXX We shouldn't ever be scheduled if
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* receive has been stopped - so complain
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* loudly!
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*/
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device_printf(sc->sc_dev,
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"%s: sc_rx_resetted=1! Bad!\n",
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__func__);
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ATH_RX_UNLOCK(sc);
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return;
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}
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#endif
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do {
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bf = re->m_fifo[re->m_fifo_head];
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/* This shouldn't occur! */
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@ -451,24 +476,6 @@ ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
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"ath edma rx proc: npkts=%d\n",
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npkts);
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/* Handle resched and kickpcu appropriately */
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ATH_PCU_LOCK(sc);
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if (dosched && sc->sc_kickpcu) {
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ATH_KTR(sc, ATH_KTR_ERROR, 0,
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"ath_edma_recv_proc_queue(): kickpcu");
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if (npkts > 0)
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device_printf(sc->sc_dev,
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"%s: handled npkts %d\n",
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__func__, npkts);
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/*
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* XXX TODO: what should occur here? Just re-poke and
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* re-enable the RX FIFO?
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*/
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sc->sc_kickpcu = 0;
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}
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ATH_PCU_UNLOCK(sc);
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return;
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}
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@ -566,6 +566,8 @@ struct ath_softc {
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int sc_tx_statuslen;
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int sc_tx_nmaps; /* Number of TX maps */
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int sc_edma_bufsize;
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int sc_rx_stopped; /* XXX only for EDMA */
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int sc_rx_resetted; /* XXX only for EDMA */
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void (*sc_node_cleanup)(struct ieee80211_node *);
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void (*sc_node_free)(struct ieee80211_node *);
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