Disable hwpmc(4) support for Intel Xeon Sandy Bridge (Model 0x2D).

Due to some differences in MSRs between Xeon Sandy Bridge and Core Sandy
Bridge (Model 0x2A), wrmsr() may generate in a GP# fault exception and so a
panic of the machine.

Approved by:		gnn (mentor)
MFC after:		3 days

sys/dev/hwpmc/hwpmc_intel.c

@@ -143,7 +143,6 @@ pmc_intel_initialize(void)
 			nclasses = 5;
 			break;
 		case 0x2A:	/* Per Intel document 253669-039US 05/2011. */
-		case 0x2D:	/* Per Intel document 253669-041US 12/2011. */	
 			cputype = PMC_CPU_INTEL_SANDYBRIDGE;
 			nclasses = 5;
 			break;