Add driver for DM9000 Ethernet MAC Controller.
This device found in the Ingenic jz4780 SoC. Submitted by: kan Sponsored by: DARPA, AFRL
This commit is contained in:
Ruslan Bukin
parent
72180f17a7
commit
f3b37a1f47
@ -1402,6 +1402,7 @@ dev/dcons/dcons.c optional dcons
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dev/dcons/dcons_crom.c optional dcons_crom
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dev/dcons/dcons_os.c optional dcons
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dev/de/if_de.c optional de pci
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dev/dme/if_dme.c optional dme
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dev/dpt/dpt_eisa.c optional dpt eisa
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dev/dpt/dpt_pci.c optional dpt pci
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dev/dpt/dpt_scsi.c optional dpt
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1070
sys/dev/dme/if_dme.c
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1070
sys/dev/dme/if_dme.c
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File diff suppressed because it is too large
Load Diff
137
sys/dev/dme/if_dmereg.h
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137
sys/dev/dme/if_dmereg.h
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@ -0,0 +1,137 @@
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/*
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* Copyright (C) 2010 Andrew Turner
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __IF_DMEREG_H__
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#define __IF_DMEREG_H__
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/*
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* DM9000 register definitions
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*/
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#define DME_NCR 0x00
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#define NCR_EXT_PHY (1<<7)
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#define NCR_WAKEEN (1<<6)
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#define NCR_FCOL (1<<4)
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#define NCR_FDX (1<<3)
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#define NCR_LBK_NORMAL (0<<1)
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#define NCR_LBK_MAC (1<<1)
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#define NCR_LBK_PHY (2<<1)
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#define NCR_RST (1<<0)
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#define DME_NSR 0x01
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#define NSR_SPEED (1<<7)
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#define NSR_LINKST (1<<6)
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#define NSR_WAKEST (1<<5)
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#define NSR_TX2END (1<<3)
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#define NSR_TX1END (1<<2)
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#define NSR_RXOV (1<<1)
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#define DME_TCR 0x02
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#define TCR_TJDIS (1<<6)
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#define TCR_EXCECM (1<<5)
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#define TCR_PAD_DIS2 (1<<4)
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#define TCR_PAD_CRC2 (1<<3)
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#define TCR_PAD_DIS1 (1<<2)
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#define TCR_PAD_CRC1 (1<<1)
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#define TCR_TXREQ (1<<0)
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#define DME_TSR1 0x03
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#define DME_TSR2 0x04
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#define DME_RCR 0x05
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#define RCR_WTDIS (1<<6)
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#define RCR_DIS_LONG (1<<5)
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#define RCR_DIS_CRC (1<<4)
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#define RCR_ALL (1<<3)
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#define RCR_RUNT (1<<2)
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#define RCR_PRMSC (1<<1)
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#define RCR_RXEN (1<<0)
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#define DME_RSR 0x06
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#define DME_ROCR 0x07
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#define DME_BPTR 0x08
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#define BPTR_BPHW(v) (((v) & 0x0f) << 4)
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#define BPTR_JPT(v) (((v) & 0x0f) << 0)
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#define DME_FCTR 0x09
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#define FCTR_HWOT(v) (((v) & 0x0f) << 4)
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#define FCTR_LWOT(v) (((v) & 0x0f) << 0)
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#define DME_FCR 0x0A
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#define DME_EPCR 0x0B
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#define EPCR_REEP (1<<5)
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#define EPCR_WEP (1<<4)
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#define EPCR_EPOS (1<<3)
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#define EPCR_ERPRR (1<<2)
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#define EPCR_ERPRW (1<<1)
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#define EPCR_ERRE (1<<0)
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#define DME_EPAR 0x0C
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#define DME_EPDRL 0x0D
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#define DME_EPDRH 0x0E
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#define DME_WCR 0x0F
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#define DME_PAR_BASE 0x10
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#define DME_PAR(n) (DME_PAR_BASE + n)
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#define DME_MAR_BASE 0x16
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#define DME_MAR(n) (DME_MAR_BASE + n)
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#define DME_GPCR 0x1E
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#define DME_GPR 0x1F
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#define DME_TRPAL 0x22
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#define DME_TRPAH 0x23
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#define DME_RWPAL 0x24
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#define DME_RWPAH 0x25
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#define DME_VIDL 0x28
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#define DME_VIDH 0x29
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#define DME_PIDL 0x2A
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#define DME_PIDH 0x2B
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#define DME_CHIPR 0x2C
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#define DME_SMCR 0x2F
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#define DME_MRCMDX 0xF0
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#define DME_MRCMD 0xF2
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#define DME_MRRL 0xF4
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#define DME_MRRH 0xF5
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#define DME_MWCMDX 0xF6
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#define DME_MWCMD 0xF8
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#define DME_MWRL 0xFA
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#define DME_MWRH 0xFB
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#define DME_TXPLL 0xFC
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#define DME_TXPLH 0xFD
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#define DME_ISR 0xFE
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#define ISR_LNKCHG (1<<5)
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#define ISR_UDRUN (1<<4)
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#define ISR_ROO (1<<3)
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#define ISR_ROS (1<<2)
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#define ISR_PT (1<<1)
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#define ISR_PR (1<<0)
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#define DME_IMR 0xFF
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#define IMR_PAR (1<<7)
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#define IMR_LNKCHGI (1<<5)
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#define IMR_UDRUNI (1<<4)
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#define IMR_ROOI (1<<3)
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#define IMR_ROI (1<<2)
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#define IMR_PTI (1<<1)
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#define IMR_PRI (1<<0)
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/* Extra PHY register from DM9000B */
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#define MII_DME_DSPCR 0x1B
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#define DSPCR_INIT 0xE100
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#endif /* __DMEREGS_H__ */
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39
sys/dev/dme/if_dmevar.h
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39
sys/dev/dme/if_dmevar.h
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@ -0,0 +1,39 @@
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/*
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* Copyright (C) 2010 Andrew Turner
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __IF_DMEVAR_H__
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#define __IF_DMEVAR_H__
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#define DME_LOCK(cs) mtx_lock(&(sc)->dme_mtx)
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#define DME_UNLOCK(cs) mtx_unlock(&(sc)->dme_mtx)
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#define DME_ASSERT_LOCKED(sc) mtx_assert(&(sc)->dme_mtx, MA_OWNED);
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#define DME_TIMEOUT 1000
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#endif /* __IF_DMEVAR_H__ */
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