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pci_host_generic: remove unneeded ThunderX2 quirk

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The current quirk implementation writes a fixed address to the PCI BAR
to fix a firmware bug. The PCI BARs are allocated by firmware and will
change depending on PCI devices present. So using a fixed address here
is not correct.

This quirk worked around a firmware bug that programmed the MSI-X bar
of the SATA controller incorrectly. The newer firmware does not have
this issue, so it is better to drop this quirk altogether.

Reviewed by:	andrew
Differential Revision:	https://reviews.freebsd.org/D17655
This commit is contained in:
Jayachandran C. 2018-11-19 02:38:02 +00:00
parent 9c1535e9ab
commit f3c5181ab9
1 changed files with 0 additions and 99 deletions
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99
sys/dev/pci/pci_host_generic.c
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@ -69,25 +69,6 @@ __FBSDID("$FreeBSD$");
(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \
((reg) & PCIE_REG_MASK))
typedef void (*pci_host_generic_quirk_function)(device_t);
struct pci_host_generic_quirk_entry {
int impl;
int part;
int var;
int rev;
pci_host_generic_quirk_function func;
};
struct pci_host_generic_block_entry {
int impl;
int part;
int var;
int rev;
int bus;
int slot;
};
/* Forward prototypes */
static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
@ -100,24 +81,6 @@ static int generic_pcie_read_ivar(device_t dev, device_t child, int index,
static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
uintptr_t value);
#if defined(__aarch64__)
static void pci_host_generic_apply_quirks(device_t);
static void thunderx2_ahci_bar_quirk(device_t);
struct pci_host_generic_quirk_entry pci_host_generic_quirks[] =
{
{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, thunderx2_ahci_bar_quirk},
{0, 0, 0, 0, NULL}
};
struct pci_host_generic_block_entry pci_host_generic_blocked[] =
{
/* ThunderX2 AHCI on second socket */
{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, 0x80, 0x10},
{0, 0, 0, 0, 0, 0}
};
#endif
int
pci_host_generic_core_attach(device_t dev)
{
@ -171,34 +134,9 @@ pci_host_generic_core_attach(device_t dev)
return (error);
}
#if defined(__aarch64__)
pci_host_generic_apply_quirks(dev);
#endif
return (0);
}
#if defined(__aarch64__)
static void
pci_host_generic_apply_quirks(device_t dev)
{
struct pci_host_generic_quirk_entry *quirk;
quirk = pci_host_generic_quirks;
while (1) {
if (quirk->impl == 0)
break;
if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
quirk->impl, quirk->part, quirk->var, quirk->rev) &&
quirk->func != NULL)
quirk->func(dev);
quirk++;
}
}
#endif
static uint32_t
generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes)
@ -208,29 +146,11 @@ generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
bus_space_tag_t t;
uint64_t offset;
uint32_t data;
#if defined(__aarch64__)
struct pci_host_generic_block_entry *block;
#endif
if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
return (~0U);
#if defined(__aarch64__)
block = pci_host_generic_blocked;
while (1) {
if (block->impl == 0)
break;
if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
block->impl, block->part, block->var, block->rev) &&
block->bus == bus && block->slot == slot)
return (~0);
block++;
}
#endif
sc = device_get_softc(dev);
offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
@ -472,22 +392,3 @@ static device_method_t generic_pcie_methods[] = {
DEFINE_CLASS_0(pcib, generic_pcie_core_driver,
generic_pcie_methods, sizeof(struct generic_pcie_core_softc));
#if defined(__aarch64__)
static void thunderx2_ahci_bar_quirk(device_t dev)
{
/*
* XXX:
* On ThunderX2, AHCI BAR2 address is wrong. It needs to precisely
* match the one described in datasheet. Fixup it unconditionally.
*/
if (device_get_unit(dev) == 0) {
device_printf(dev, "running AHCI BAR fixup\n");
PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x18, 0x01440000, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x1c, 0x40, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x18, 0x01450000, 4);
PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x1c, 0x40, 4);
}
}
#endif