From f3e8efe2d48958d1c844c2d1bc4ac22b04404ebc Mon Sep 17 00:00:00 2001 From: alc Date: Thu, 11 Jul 2019 02:43:23 +0000 Subject: [PATCH] According to Section D5.10.3 "Maintenance requirements on changing System register values" of the architecture manual, an isb instruction should be executed after updating ttbr0_el1 and before invalidating the TLB. The lack of this instruction in pmap_activate() appears to be the reason why andrew@ and I have observed an unexpected TLB entry for an invalid PTE on entry to pmap_enter_quick_locked(). Thus, we should now be able to revert the workaround committed in r349442. Reviewed by: markj MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D20904 --- sys/arm64/arm64/efirt_machdep.c | 2 ++ sys/arm64/arm64/pmap.c | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/sys/arm64/arm64/efirt_machdep.c b/sys/arm64/arm64/efirt_machdep.c index 50de8a4d343c..658f03696c22 100644 --- a/sys/arm64/arm64/efirt_machdep.c +++ b/sys/arm64/arm64/efirt_machdep.c @@ -239,6 +239,7 @@ efi_arch_enter(void) __asm __volatile( "msr ttbr0_el1, %0 \n" + "isb \n" "dsb ishst \n" "tlbi vmalle1is \n" "dsb ish \n" @@ -266,6 +267,7 @@ efi_arch_leave(void) td = curthread; __asm __volatile( "msr ttbr0_el1, %0 \n" + "isb \n" "dsb ishst \n" "tlbi vmalle1is \n" "dsb ish \n" diff --git a/sys/arm64/arm64/pmap.c b/sys/arm64/arm64/pmap.c index f8ae0427becd..31f5552931c3 100644 --- a/sys/arm64/arm64/pmap.c +++ b/sys/arm64/arm64/pmap.c @@ -5484,8 +5484,10 @@ pmap_activate(struct thread *td) critical_enter(); pmap = vmspace_pmap(td->td_proc->p_vmspace); td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0); - __asm __volatile("msr ttbr0_el1, %0" : : - "r"(td->td_proc->p_md.md_l0addr)); + __asm __volatile( + "msr ttbr0_el1, %0 \n" + "isb \n" + : : "r"(td->td_proc->p_md.md_l0addr)); pmap_invalidate_all(pmap); critical_exit(); }