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move awi to the Attic; it will not make the jump to the new world order

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Reviewed by:	imp
This commit is contained in:
Sam Leffler 2008-04-20 19:20:39 +00:00
parent aae6cab8a8
commit f446360711
20 changed files with 1 additions and 3942 deletions
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2
share/man/man4/Makefile
View File

@ -32,7 +32,6 @@ MAN= aac.4 \
audit.4 \
auditpipe.4 \
aue.4 \
awi.4 \
axe.4 \
bce.4 \
bfe.4 \
@ -436,7 +435,6 @@ MLINKS+=ata.4 acd.4 \
ata.4 afd.4 \
ata.4 ast.4
MLINKS+=aue.4 if_aue.4
MLINKS+=awi.4 if_awi.4
MLINKS+=axe.4 if_axe.4
MLINKS+=bce.4 if_bce.4
MLINKS+=bfe.4 if_bfe.4

1
share/man/man4/altq.4
View File

@ -118,7 +118,6 @@ They have been applied to the following hardware drivers:
.Xr an 4 ,
.Xr ath 4 ,
.Xr aue 4 ,
.Xr awi 4 ,
.Xt axe 4 ,
.Xr bce 4 ,
.Xr bfe 4 ,

155
share/man/man4/awi.4
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@ -1,155 +0,0 @@
.\" $NetBSD: awi.4,v 1.6 2000/03/22 11:24:33 onoe Exp $
.\" $FreeBSD$
.\"
.Dd July 16, 2005
.Dt AWI 4
.Os
.Sh NAME
.Nm awi
.Nd "AMD PCnetMobile IEEE 802.11 PCMCIA wireless network driver"
.Sh SYNOPSIS
To compile this driver into the kernel,
place the following lines in your
kernel configuration file:
.Bd -ragged -offset indent
.Cd "device awi"
.Cd "device wlan"
.Ed
.Pp
Alternatively, to load the driver as a
module at boot time, place the following line in
.Xr loader.conf 5 :
.Bd -literal -offset indent
if_awi_load="YES"
.Ed
.Sh DESCRIPTION
The
.Nm
driver supports various IEEE 802.11 wireless cards
which run AMD PCnetMobile firmware based on AMD 79c930 controller
with Intersil (formerly Harris) PRISM radio chipset.
It provides access to 32kb of memory shared between the controller
and the host.
All host/device interaction is via this shared memory, which can be
accessed either via PCMCIA memory space or I/O space.
The
.Nm
driver encapsulates all IP and ARP traffic as 802.11 frames.
.Pp
The driver works both in infrastructure mode and in adhoc (independent
BSS) mode.
.Pp
In infrastructure mode, it communicates with an Access Point
which serves as a link-layer bridge between an Ethernet and
the wireless network.
An access point also provides roaming capability
which allows wireless nodes to move between access points.
.Pp
In adhoc mode, it communicates peer to peer.
Though it is more efficient to communicate between wireless nodes,
the coverage is limited spatially due to lack of roaming capability.
.Pp
In addition to these two modes in the IEEE 802.11 specification, the
.Nm
driver also supports a variant of adhoc mode out of spec for DS radio cards,
which makes it possible to communicate with adhoc mode of
.Xr wi 4
driver.
The NWID does not affect in this mode.
.Pp
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh HARDWARE
Cards supported by the
.Nm
driver include:
.Pp
.Bl -tag -width BayStack_650x -offset indent
.It BayStack 650
1Mbps Frequency Hopping PCCARD adapter
.It BayStack 660
2Mbps Direct Sequence PCCARD adapter
.It Icom SL-200
2Mbps Direct Sequence PCCARD adapter
.It Melco WLI-PCM
2Mbps Direct Sequence PCCARD adapter
.It NEL SSMagic
2Mbps Direct Sequence PCCARD adapter
.It Netwave AirSurfer Plus
1Mbps Frequency Hopping PCCARD adapter
.It Netwave AirSurfer Pro
2Mbps Direct Sequence PCCARD adapter
.It Nokia C020 WLAN
2Mbps Direct Sequence PCCARD adapter
.It Farallon SkyLINE
2Mbps Direct Sequence PCCARD adapter
.El
.Pp
The original Xircom Netwave AirSurfer is supported by the
.Xr cnw 4
driver.
.Sh MEDIA SELECTION
The DS cards support
.Em DS1
and
.Em DS2
media types, while the FH cards support
.Em FH1
media type.
For each media type,
.Em adhoc
mediaopt can be used to indicate the driver to operate in adhoc mode.
For DS radio cards,
.Em adhoc , Ns Em flag0
mediaopt can be used for
.Xr wi 4
compatible adhoc mode.
In addition to these station modes,
.Em hostap
mediaopt can be used to create a host-based access point.
.Sh DIAGNOSTICS
.Bl -diag
.It "awi0: awi_pccard_probe: bad banner:"
The device failed to initialize its firmware.
.It "awi0: failed to complete selftest (%s)"
The device failed to complete its self test.
In some circumstances, resetting device after power on fails.
Re-inserting the card or down-then-up interface may be helpful.
.It "awi0: transmit timeout"
The device failed to generate an interrupt to acknowledge a
transmitted packet.
.It "awi0: failed to lock interrupt"
The system was unable to obtain the lock to access shared memory.
.It "awi0: command %d failed %x"
The device failed to complete the request from the system.
.El
.Sh SEE ALSO
.Xr altq 4 ,
.Xr arp 4 ,
.Xr cnw 4 ,
.Xr miibus 4 ,
.Xr netintro 4 ,
.Xr pccard 4 ,
.Xr wi 4 ,
.Xr wlan 4 ,
.Xr ifconfig 8
.Rs
.%T Am79C930 PCnet Mobile Single-Chip Wireless LAN Media Access Controller
.%O http://www.amd.com
.Re
.Sh HISTORY
The
.Nm
device driver first appeared in
.Nx 1.5 .
.Sh AUTHORS
.An -nosplit
The initial version of the
.Nm
driver was written by
.An Bill Sommerfeld Aq sommerfeld@netbsd.org .
Then the
.Nm
driver module was completely rewritten to support cards with DS phy and
to support adhoc mode by
.An Atsushi Onoe Aq onoe@netbsd.org .

4
share/man/man4/cnw.4
View File

@ -56,9 +56,6 @@ Note that the driver does not support newer devices
such as the Netwave AirSurfer
.Dq Plus ,
or the BayStack 650/660.
These devices are supported by the
.Xr awi 4
driver.
.Pp
Netwave devices are not compatible with IEEE 802.11 wireless networks.
Also note that there are Netwave devices with different wireless frequency,
@ -106,7 +103,6 @@ and increase memory available to the PC Card controller.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr awi 4 ,
.Xr inet 4 ,
.Xr intro 4 ,
.Xr pccard 4

2
share/man/man4/wlan.4
View File

@ -44,7 +44,6 @@ The
is required for the
.Xr an 4 ,
.Xr ath 4 ,
.Xr awi 4 ,
.Xr ipw 4 ,
.Xr iwi 4 ,
.Xr ral 4 ,
@ -123,7 +122,6 @@ was used to be compatible with
.Sh SEE ALSO
.Xr an 4 ,
.Xr ath 4 ,
.Xr awi 4 ,
.Xr ipw 4 ,
.Xr iwi 4 ,
.Xr netintro 4 ,

1
sys/amd64/conf/GENERIC
View File

@ -245,7 +245,6 @@ device an # Aironet 4500/4800 802.11 wireless NICs.
device ath # Atheros pci/cardbus NIC's
device ath_hal # Atheros HAL (Hardware Access Layer)
device ath_rate_sample # SampleRate tx rate control for ath
device awi # BayStack 660 and others
device ral # Ralink Technology RT2500 wireless NICs.
device wi # WaveLAN/Intersil/Symbol 802.11 wireless NICs.

5
sys/conf/NOTES
View File

@ -707,7 +707,7 @@ device mn # Munich32x/Falc54 Nx64kbit/sec cards.
# according to IEEE 802.1Q. It requires `device miibus'.
# The `wlan' device provides generic code to support 802.11
# drivers, including host AP mode; it is MANDATORY for the wi,
# ath, and awi drivers and will eventually be required by all 802.11 drivers.
# and ath drivers and will eventually be required by all 802.11 drivers.
# The `wlan_wep', `wlan_tkip', and `wlan_ccmp' devices provide
# support for WEP, TKIP, and AES-CCMP crypto protocols optionally
# used with 802.11 devices that depend on the `wlan' module.
@ -1744,8 +1744,6 @@ device miibus
# an: Aironet 4500/4800 802.11 wireless adapters. Supports the PCMCIA,
# PCI and ISA varieties.
# awi: Support for IEEE 802.11 PC Card devices using the AMD Am79C930 and
# Harris (Intersil) Chipset with PCnetMobile firmware by AMD.
# bce: Broadcom NetXtreme II (BCM5706/BCM5708) PCI/PCIe Gigabit Ethernet
# adapters.
# bfe: Broadcom BCM4401 Ethernet adapter.
@ -1881,7 +1879,6 @@ hint.sn.0.at="isa"
hint.sn.0.port="0x300"
hint.sn.0.irq="10"
device an
device awi
device cnw
device wi
device xe

3
sys/conf/files
View File

@ -486,9 +486,6 @@ dev/ath/if_ath.c optional ath \
compile-with "${NORMAL_C} -I$S/dev/ath"
dev/ath/if_ath_pci.c optional ath pci \
compile-with "${NORMAL_C} -I$S/dev/ath"
dev/awi/am79c930.c optional awi
dev/awi/awi.c optional awi
dev/awi/if_awi_pccard.c optional awi pccard
dev/bce/if_bce.c optional bce
dev/bfe/if_bfe.c optional bfe
dev/bge/if_bge.c optional bge

419
sys/dev/awi/am79c930.c
View File

@ -1,419 +0,0 @@
/* $NetBSD: am79c930.c,v 1.9 2004/01/15 09:33:48 onoe Exp $ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Bill Sommerfeld
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Am79c930 chip driver.
*
* This is used by the awi driver to use the shared
* memory attached to the 79c930 to communicate with the firmware running
* in the 930's on-board 80188 core.
*
* The 79c930 can be mapped into just I/O space, or also have a
* memory mapping; the mapping must be set up by the bus front-end
* before am79c930_init is called.
*/
/*
* operations:
*
* read_8, read_16, read_32, read_64, read_bytes
* write_8, write_16, write_32, write_64, write_bytes
* (two versions, depending on whether memory-space or i/o space is in use).
*
* interrupt E.C.
* start isr
* end isr
*/
#include <sys/cdefs.h>
#ifdef __NetBSD__
__KERNEL_RCSID(0, "$NetBSD: am79c930.c,v 1.9 2004/01/15 09:33:48 onoe Exp $");
#endif
#ifdef __FreeBSD__
__FBSDID("$FreeBSD$");
#endif
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/endian.h>
#ifndef __FreeBSD__
#include <sys/device.h>
#endif
#include <machine/cpu.h>
#include <machine/bus.h>
#ifdef __NetBSD__
#include <machine/intr.h>
#endif
#ifdef __NetBSD__
#include <dev/ic/am79c930reg.h>
#include <dev/ic/am79c930var.h>
#endif
#ifdef __FreeBSD__
#include <dev/awi/am79c930reg.h>
#include <dev/awi/am79c930var.h>
#endif
#define AM930_DELAY(x) /*nothing*/
void am79c930_regdump(struct am79c930_softc *sc);
static void io_write_1(struct am79c930_softc *, u_int32_t, u_int8_t);
static void io_write_2(struct am79c930_softc *, u_int32_t, u_int16_t);
static void io_write_4(struct am79c930_softc *, u_int32_t, u_int32_t);
static void io_write_bytes(struct am79c930_softc *, u_int32_t, u_int8_t *, size_t);
static u_int8_t io_read_1(struct am79c930_softc *, u_int32_t);
static u_int16_t io_read_2(struct am79c930_softc *, u_int32_t);
static u_int32_t io_read_4(struct am79c930_softc *, u_int32_t);
static void io_read_bytes(struct am79c930_softc *, u_int32_t, u_int8_t *, size_t);
static void mem_write_1(struct am79c930_softc *, u_int32_t, u_int8_t);
static void mem_write_2(struct am79c930_softc *, u_int32_t, u_int16_t);
static void mem_write_4(struct am79c930_softc *, u_int32_t, u_int32_t);
static void mem_write_bytes(struct am79c930_softc *, u_int32_t, u_int8_t *, size_t);
static u_int8_t mem_read_1(struct am79c930_softc *, u_int32_t);
static u_int16_t mem_read_2(struct am79c930_softc *, u_int32_t);
static u_int32_t mem_read_4(struct am79c930_softc *, u_int32_t);
static void mem_read_bytes(struct am79c930_softc *, u_int32_t, u_int8_t *, size_t);
static struct am79c930_ops iospace_ops = {
io_write_1,
io_write_2,
io_write_4,
io_write_bytes,
io_read_1,
io_read_2,
io_read_4,
io_read_bytes
};
struct am79c930_ops memspace_ops = {
mem_write_1,
mem_write_2,
mem_write_4,
mem_write_bytes,
mem_read_1,
mem_read_2,
mem_read_4,
mem_read_bytes
};
static void
io_write_1( struct am79c930_softc *sc, u_int32_t off, u_int8_t val)
{
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_HI,
((off>>8)& 0x7f));
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_LO, (off&0xff));
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA, val);
AM930_DELAY(1);
}
static void
io_write_2(struct am79c930_softc *sc, u_int32_t off, u_int16_t val)
{
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_HI,
((off>>8)& 0x7f));
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_LMA_LO, (off&0xff));
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA, val & 0xff);
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA, (val>>8)&0xff);
AM930_DELAY(1);
}
static void
io_write_4(struct am79c930_softc *sc, u_int32_t off, u_int32_t val)
{
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_HI,
((off>>8)& 0x7f));
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_LMA_LO, (off&0xff));
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA,val & 0xff);
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA,(val>>8)&0xff);
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA,(val>>16)&0xff);
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA,(val>>24)&0xff);
AM930_DELAY(1);
}
static void
io_write_bytes(struct am79c930_softc *sc, u_int32_t off, u_int8_t *ptr,
size_t len)
{
int i;
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_HI,
((off>>8)& 0x7f));
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_LMA_LO, (off&0xff));
AM930_DELAY(1);
for (i=0; i<len; i++)
bus_space_write_1(sc->sc_iot,sc->sc_ioh,AM79C930_IODPA,ptr[i]);
}
static u_int8_t
io_read_1(struct am79c930_softc *sc, u_int32_t off)
{
u_int8_t val;
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_HI,
((off>>8)& 0x7f));
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_LO, (off&0xff));
AM930_DELAY(1);
val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA);
AM930_DELAY(1);
return val;
}
static u_int16_t
io_read_2(struct am79c930_softc *sc, u_int32_t off)
{
u_int16_t val;
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_HI,
((off>>8)& 0x7f));
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_LO, (off&0xff));
AM930_DELAY(1);
val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA);
AM930_DELAY(1);
val |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA) << 8;
AM930_DELAY(1);
return val;
}
static u_int32_t
io_read_4(struct am79c930_softc *sc, u_int32_t off)
{
u_int32_t val;
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_HI,
((off>>8)& 0x7f));
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_LO, (off&0xff));
AM930_DELAY(1);
val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA);
AM930_DELAY(1);
val |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA) << 8;
AM930_DELAY(1);
val |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA) << 16;
AM930_DELAY(1);
val |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, AM79C930_IODPA) << 24;
AM930_DELAY(1);
return val;
}
static void
io_read_bytes(struct am79c930_softc *sc, u_int32_t off, u_int8_t *ptr,
size_t len)
{
int i;
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_HI,
((off>>8)& 0x7f));
AM930_DELAY(1);
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_LMA_LO, (off&0xff));
AM930_DELAY(1);
for (i=0; i<len; i++)
ptr[i] = bus_space_read_1(sc->sc_iot, sc->sc_ioh,
AM79C930_IODPA);
}
static void
mem_write_1(struct am79c930_softc *sc, u_int32_t off, u_int8_t val)
{
bus_space_write_1(sc->sc_memt, sc->sc_memh, off, val);
}
static
void mem_write_2(struct am79c930_softc *sc, u_int32_t off, u_int16_t val)
{
bus_space_tag_t t = sc->sc_memt;
bus_space_handle_t h = sc->sc_memh;
/* could be unaligned */
if ((off & 0x1) == 0)
bus_space_write_2(t, h, off, htole16(val));
else {
bus_space_write_1(t, h, off, val & 0xff);
bus_space_write_1(t, h, off+1, (val >> 8) & 0xff);
}
}
static void
mem_write_4(struct am79c930_softc *sc, u_int32_t off, u_int32_t val)
{
bus_space_tag_t t = sc->sc_memt;
bus_space_handle_t h = sc->sc_memh;
/* could be unaligned */
if ((off & 0x3) == 0)
bus_space_write_4(t, h, off, htole32(val));
else {
bus_space_write_1(t, h, off, val & 0xff);
bus_space_write_1(t, h, off+1, (val >> 8) & 0xff);
bus_space_write_1(t, h, off+2, (val >> 16) & 0xff);
bus_space_write_1(t, h, off+3, (val >> 24) & 0xff);
}
}
static void
mem_write_bytes(struct am79c930_softc *sc, u_int32_t off, u_int8_t *ptr,
size_t len)
{
bus_space_write_region_1 (sc->sc_memt, sc->sc_memh, off, ptr, len);
}
static u_int8_t
mem_read_1(struct am79c930_softc *sc, u_int32_t off)
{
return bus_space_read_1(sc->sc_memt, sc->sc_memh, off);
}
static u_int16_t
mem_read_2(struct am79c930_softc *sc, u_int32_t off)
{
/* could be unaligned */
if ((off & 0x1) == 0)
return le16toh(bus_space_read_2(sc->sc_memt, sc->sc_memh, off));
else
return
bus_space_read_1(sc->sc_memt, sc->sc_memh, off ) |
(bus_space_read_1(sc->sc_memt, sc->sc_memh, off+1) << 8);
}
static u_int32_t
mem_read_4(struct am79c930_softc *sc, u_int32_t off)
{
/* could be unaligned */
if ((off & 0x3) == 0)
return le32toh(bus_space_read_4(sc->sc_memt, sc->sc_memh, off));
else
return
bus_space_read_1(sc->sc_memt, sc->sc_memh, off ) |
(bus_space_read_1(sc->sc_memt, sc->sc_memh, off+1) << 8) |
(bus_space_read_1(sc->sc_memt, sc->sc_memh, off+2) <<16) |
(bus_space_read_1(sc->sc_memt, sc->sc_memh, off+3) <<24);
}
static void
mem_read_bytes(struct am79c930_softc *sc, u_int32_t off, u_int8_t *ptr,
size_t len)
{
bus_space_read_region_1 (sc->sc_memt, sc->sc_memh, off, ptr, len);
}
/*
* Set bits in GCR.
*/
void
am79c930_gcr_setbits(struct am79c930_softc *sc, u_int8_t bits)
{
u_int8_t gcr = bus_space_read_1 (sc->sc_iot, sc->sc_ioh, AM79C930_GCR);
gcr |= bits;
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_GCR, gcr);
}
/*
* Clear bits in GCR.
*/
void
am79c930_gcr_clearbits(struct am79c930_softc *sc, u_int8_t bits)
{
u_int8_t gcr = bus_space_read_1 (sc->sc_iot, sc->sc_ioh, AM79C930_GCR);
gcr &= ~bits;
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_GCR, gcr);
}
u_int8_t
am79c930_gcr_read(struct am79c930_softc *sc)
{
return bus_space_read_1 (sc->sc_iot, sc->sc_ioh, AM79C930_GCR);
}
#if 0
void
am79c930_regdump(struct am79c930_softc *sc)
{
u_int8_t buf[8];
int i;
AM930_DELAY(5);
for (i=0; i<8; i++) {
buf[i] = bus_space_read_1 (sc->sc_iot, sc->sc_ioh, i);
AM930_DELAY(5);
}
printf("am79c930: regdump:");
for (i=0; i<8; i++) {
printf(" %02x", buf[i]);
}
printf("\n");
}
#endif
void
am79c930_chip_init(struct am79c930_softc *sc, int how)
{
/* zero the bank select register, and leave it that way.. */
bus_space_write_1(sc->sc_iot, sc->sc_ioh, AM79C930_BSS, 0);
if (how)
sc->sc_ops = &memspace_ops;
else
sc->sc_ops = &iospace_ops;
}

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sys/dev/awi/am79c930reg.h
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/* $NetBSD: am79c930reg.h,v 1.4 2003/11/02 11:07:45 wiz Exp $ */
/* $FreeBSD$ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Bill Sommerfeld
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Device register definitions gleaned from from the AMD "Am79C930
* PCnet(tm)-Mobile Single Chip Wireless LAN Media Access Controller"
* data sheet, AMD Pub #20183, Rev B, amendment/0, issue date August 1997.
*
* As of 1999/10/23, this was available from AMD's web site in PDF
* form.
*/
/*
* The 79c930 contains a bus interface unit, a media access
* controller, and a tranceiver attachment interface.
* The MAC contains an 80188 CPU core.
* typical devices built around this chip typically add 32k or 64k of
* memory for buffers.
*
* The 80188 runs firmware which handles most of the 802.11 gorp, and
* communicates with the host using shared data structures in this
* memory; the specifics of the shared memory layout are not covered
* in this source file; see <dev/ic/am80211fw.h> for details of that layer.
*/
/*
* Device Registers
*/
#define AM79C930_IO_BASE 0
#define AM79C930_IO_SIZE 16
#define AM79C930_IO_SIZE_BIG 40
#define AM79C930_IO_ALIGN 0x40 /* am79c930 decodes lower 6bits */
#define AM79C930_GCR 0 /* General Config Register */
#define AM79C930_GCR_SWRESET 0x80 /* software reset */
#define AM79C930_GCR_CORESET 0x40 /* core reset */
#define AM79C930_GCR_DISPWDN 0x20 /* disable powerdown */
#define AM79C930_GCR_ECWAIT 0x10 /* embedded controller wait */
#define AM79C930_GCR_ECINT 0x08 /* interrupt from embedded ctrlr */
#define AM79C930_GCR_INT2EC 0x04 /* interrupt to embedded ctrlr */
#define AM79C930_GCR_ENECINT 0x02 /* enable interrupts from e.c. */
#define AM79C930_GCR_DAM 0x01 /* direct access mode (read only) */
#define AM79C930_GCR_BITS "\020\1DAM\2ENECINT\3INT2EC\4ECINT\5ECWAIT\6DISPWDN\7CORESET\010SWRESET"
#define AM79C930_BSS 1 /* Bank Switching Select register */
#define AM79C930_BSS_ECATR 0x80 /* E.C. ALE test read */
#define AM79C930_BSS_FS 0x20 /* Flash Select */
#define AM79C930_BSS_MBS 0x18 /* Memory Bank Select */
#define AM79C930_BSS_EIOW 0x04 /* Expand I/O Window */
#define AM79C930_BSS_TBS 0x03 /* TAI Bank Select */
#define AM79C930_LMA_LO 2 /* Local Memory Address register (low byte) */
#define AM79C930_LMA_HI 3 /* Local Memory Address register (high byte) */
/* set this bit to turn off ISAPnP version */
#define AM79C930_LMA_HI_ISAPWRDWN 0x80
/*
* mmm, inconsistency in chip documentation:
* According to page 79--80, all four of the following are equivalent
* and address the single byte pointed at by BSS_{FS,MBS} | LMA_{HI,LO}
* According to tables on p63 and p67, they're the LSB through MSB
* of a 32-bit word.
*/
#define AM79C930_IODPA 4 /* I/O Data port A */
#define AM79C930_IODPB 5 /* I/O Data port B */
#define AM79C930_IODPC 6 /* I/O Data port C */
#define AM79C930_IODPD 7 /* I/O Data port D */
/*
* Tranceiver Attachment Interface Registers (TIR space)
* (omitted for now, since host access to them is for diagnostic
* purposes only).
*/
/*
* memory space goo.
*/
#define AM79C930_MEM_SIZE 0x8000 /* 32k */
#define AM79C930_MEM_BASE 0x0 /* starting at 0 */

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sys/dev/awi/am79c930var.h
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/* $NetBSD: am79c930var.h,v 1.3 2004/01/15 09:33:48 onoe Exp $ */
/* $FreeBSD$ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Bill Sommerfeld
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#define AM79C930_BUS_PCMCIA 1
#define AM79C930_BUS_ISAPNP 2 /* not implemented */
struct am79c930_softc
{
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
bus_space_tag_t sc_memt;
bus_space_handle_t sc_memh;
struct am79c930_ops *sc_ops;
int sc_bustype;
};
struct am79c930_ops
{
void (*write_1)(struct am79c930_softc *, u_int32_t, u_int8_t);
void (*write_2)(struct am79c930_softc *, u_int32_t, u_int16_t);
void (*write_4)(struct am79c930_softc *, u_int32_t, u_int32_t);
void (*write_bytes)(struct am79c930_softc *, u_int32_t, u_int8_t *, size_t);
u_int8_t (*read_1)(struct am79c930_softc *, u_int32_t);
u_int16_t (*read_2)(struct am79c930_softc *, u_int32_t);
u_int32_t (*read_4)(struct am79c930_softc *, u_int32_t);
void (*read_bytes)(struct am79c930_softc *, u_int32_t, u_int8_t *, size_t);
};
void am79c930_chip_init(struct am79c930_softc *sc, int);
void am79c930_gcr_setbits(struct am79c930_softc *sc, u_int8_t bits);
void am79c930_gcr_clearbits(struct am79c930_softc *sc, u_int8_t bits);
u_int8_t am79c930_gcr_read(struct am79c930_softc *sc);
#define am79c930_hard_reset(sc) am79c930_gcr_setbits(sc, AM79C930_GCR_CORESET)
#define am79c930_hard_reset_off(sc) am79c930_gcr_clearbits(sc, AM79C930_GCR_CORESET)

2219
sys/dev/awi/awi.c
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sys/dev/awi/awireg.h
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/* $NetBSD: awireg.h,v 1.8 2003/01/20 05:30:06 simonb Exp $ */
/* $FreeBSD$ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Bill Sommerfeld
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _DEV_IC_AWIREG_H
#define _DEV_IC_AWIREG_H
/*
* The firmware typically loaded onto Am79C930-based 802.11 interfaces
* uses a 32k or larger shared memory buffer to communicate with the
* host.
*
* Depending on the exact configuration of the device, this buffer may
* either be mapped into PCMCIA memory space, or accessible a byte at
* a type through PCMCIA I/O space.
*
* This header defines offsets into this shared memory.
*/
/*
* LAST_TXD block. 5 32-bit words.
*
* There are five different output queues; this defines pointers to
* the last completed descriptor for each one.
*/
#define AWI_LAST_TXD 0x3ec /* last completed Tx Descr */
#define AWI_LAST_BCAST_TXD AWI_LAST_TXD+0
#define AWI_LAST_MGT_TXD AWI_LAST_TXD+4
#define AWI_LAST_DATA_TXD AWI_LAST_TXD+8
#define AWI_LAST_PS_POLL_TXD AWI_LAST_TXD+12
#define AWI_LAST_CF_POLL_TXD AWI_LAST_TXD+16
/*
* Banner block; null-terminated string.
*
* The doc says it contains
* "PCnetMobile:v2.00 mmddyy APIx.x\0"
*/
#define AWI_BANNER 0x480 /* Version string */
#define AWI_BANNER_LEN 0x20
/*
* Command block protocol:
* write command byte to a zero value.
* write command status to a zero value.
* write arguments to AWI_COMMAND_PARAMS
* write command byte to a non-zero value.
* wait for command status to be non-zero.
* write command byte to a zero value.
* write command status to a zero value.
*/
#define AWI_CMD 0x4a0 /* Command opcode byte */
#define AWI_CMD_IDLE 0x0
#define AWI_CMD_NOP 0x1
#define AWI_CMD_SET_MIB 0x2
#define AWI_CMD_GET_MIB 0x9
#define AWI_CA_MIB_TYPE (AWI_CMD_PARAMS + 0x0)
#define AWI_CA_MIB_SIZE (AWI_CMD_PARAMS + 0x1)
#define AWI_CA_MIB_INDEX (AWI_CMD_PARAMS + 0x2)
#define AWI_CA_MIB_DATA (AWI_CMD_PARAMS + 0x4)
#define AWI_MIB_LOCAL 0
#define AWI_MIB_ADDR 2
#define AWI_MIB_MAC 3
#define AWI_MIB_STAT 4
#define AWI_MIB_MGT 5
#define AWI_MIB_DRVR 6
#define AWI_MIB_PHY 7
#define AWI_CMD_INIT_TX 0x3
#define AWI_CA_TX_LEN 20
#define AWI_CA_TX_DATA (AWI_CMD_PARAMS + 0x0)
#define AWI_CA_TX_MGT (AWI_CMD_PARAMS + 0x4)
#define AWI_CA_TX_BCAST (AWI_CMD_PARAMS + 0x8)
#define AWI_CA_TX_PS (AWI_CMD_PARAMS + 0xc)
#define AWI_CA_TX_CF (AWI_CMD_PARAMS + 0x10)
#define AWI_CMD_FLUSH_TX 0x4
#define AWI_CA_FTX_LEN 5
#define AWI_CA_FTX_DATA (AWI_CMD_PARAMS + 0x0)
#define AWI_CA_FTX_MGT (AWI_CMD_PARAMS + 0x1)
#define AWI_CA_FTX_BCAST (AWI_CMD_PARAMS + 0x2)
#define AWI_CA_FTX_PS (AWI_CMD_PARAMS + 0x3)
#define AWI_CA_FTX_CF (AWI_CMD_PARAMS + 0x4)
#define AWI_CMD_INIT_RX 0x5
#define AWI_CA_IRX_LEN 0x8
#define AWI_CA_IRX_DATA_DESC (AWI_CMD_PARAMS + 0x0) /* return */
#define AWI_CA_IRX_PS_DESC (AWI_CMD_PARAMS + 0x4) /* return */
#define AWI_CMD_KILL_RX 0x6
#define AWI_CMD_SLEEP 0x7
#define AWI_CA_SLEEP_LEN 8
#define AWI_CA_WAKEUP (AWI_CMD_PARAMS + 0x0) /* uint64 */
#define AWI_CMD_WAKE 0x8
#define AWI_CMD_SCAN 0xa
#define AWI_CA_SCAN_LEN 6
#define AWI_CA_SCAN_DURATION (AWI_CMD_PARAMS + 0x0)
#define AWI_CA_SCAN_SET (AWI_CMD_PARAMS + 0x2)
#define AWI_CA_SCAN_PATTERN (AWI_CMD_PARAMS + 0x3)
#define AWI_CA_SCAN_IDX (AWI_CMD_PARAMS + 0x4)
#define AWI_CA_SCAN_SUSP (AWI_CMD_PARAMS + 0x5)
#define AWI_CMD_SYNC 0xb
#define AWI_CA_SYNC_LEN 20
#define AWI_CA_SYNC_SET (AWI_CMD_PARAMS + 0x0)
#define AWI_CA_SYNC_PATTERN (AWI_CMD_PARAMS + 0x1)
#define AWI_CA_SYNC_IDX (AWI_CMD_PARAMS + 0x2)
#define AWI_CA_SYNC_STARTBSS (AWI_CMD_PARAMS + 0x3)
#define AWI_CA_SYNC_DWELL (AWI_CMD_PARAMS + 0x4)
#define AWI_CA_SYNC_MBZ (AWI_CMD_PARAMS + 0x6)
#define AWI_CA_SYNC_TIMESTAMP (AWI_CMD_PARAMS + 0x8)
#define AWI_CA_SYNC_REFTIME (AWI_CMD_PARAMS + 0x10)
#define AWI_CMD_RESUME 0xc
#define AWI_CMD_STATUS 0x4a1 /* Command status */
#define AWI_STAT_IDLE 0x0
#define AWI_STAT_OK 0x1
#define AWI_STAT_BADCMD 0x2
#define AWI_STAT_BADPARM 0x3
#define AWI_STAT_NOTIMP 0x4
#define AWI_STAT_BADRES 0x5
#define AWI_STAT_BADMODE 0x6
#define AWI_ERROR_OFFSET 0x4a2 /* Offset to erroneous parameter */
#define AWI_CMD_PARAMS 0x4a4 /* Command parameters */
#define AWI_CSB 0x4f0 /* Control/Status block */
#define AWI_SELFTEST 0x4f0
#define AWI_SELFTEST_INIT 0x00 /* initial */
#define AWI_SELFTEST_FIRMCKSUM 0x01 /* firmware cksum running */
#define AWI_SELFTEST_HARDWARE 0x02 /* hardware tests running */
#define AWI_SELFTEST_MIB 0x03 /* mib initializing */
#define AWI_SELFTEST_MIB_FAIL 0xfa
#define AWI_SELFTEST_RADIO_FAIL 0xfb
#define AWI_SELFTEST_MAC_FAIL 0xfc
#define AWI_SELFTEST_FLASH_FAIL 0xfd
#define AWI_SELFTEST_RAM_FAIL 0xfe
#define AWI_SELFTEST_PASSED 0xff
#define AWI_STA_STATE 0x4f1
#define AWI_STA_AP 0x20 /* acting as AP */
#define AWI_STA_NOPSP 0x10 /* Power Saving disabled */
#define AWI_STA_DOZE 0x08 /* about to go to sleep */
#define AWI_STA_PSP 0x04 /* enable PSP */
#define AWI_STA_RXEN 0x02 /* enable RX */
#define AWI_STA_TXEN 0x01 /* enable TX */
#define AWI_INTSTAT 0x4f3
#define AWI_INTMASK 0x4f4
/* Bits in AWI_INTSTAT/AWI_INTMASK */
#define AWI_INT_GROGGY 0x80 /* about to wake up */
#define AWI_INT_CFP_ENDING 0x40 /* cont. free period ending */
#define AWI_INT_DTIM 0x20 /* beacon outgoing */
#define AWI_INT_CFP_START 0x10 /* cont. free period starting */
#define AWI_INT_SCAN_CMPLT 0x08 /* scan complete */
#define AWI_INT_TX 0x04 /* tx done */
#define AWI_INT_RX 0x02 /* rx done */
#define AWI_INT_CMD 0x01 /* cmd done */
/*
* The following are used to implement a locking protocol between host
* and MAC to protect the interrupt status and mask fields.
*
* driver: read lockout_host byte; if zero, set lockout_mac to non-zero,
* then reread lockout_host byte; if still zero, host has lock.
* if non-zero, clear lockout_mac, loop.
*/
#define AWI_LOCKOUT_MAC 0x4f5
#define AWI_LOCKOUT_HOST 0x4f6
#define AWI_INTSTAT2 0x4f7
#define AWI_INTMASK2 0x4fd
/* Bits in AWI_INTSTAT2/INTMASK2 */
#define AWI_INT2_RXMGT 0x80 /* mgt/ps received */
#define AWI_INT2_RXDATA 0x40 /* data received */
#define AWI_INT2_TXMGT 0x10 /* mgt tx done */
#define AWI_INT2_TXCF 0x08 /* CF tx done */
#define AWI_INT2_TXPS 0x04 /* PS tx done */
#define AWI_INT2_TXBCAST 0x02 /* Broadcast tx done */
#define AWI_INT2_TXDATA 0x01 /* data tx done */
#define AWI_DIS_PWRDN 0x4fc /* disable powerdown if set */
#define AWI_DRIVERSTATE 0x4fe /* driver state */
#define AWI_DRV_STATEMASK 0x0f
#define AWI_DRV_RESET 0x0
#define AWI_DRV_INFSY 0x1 /* inf synced */
#define AWI_DRV_ADHSC 0x2 /* adhoc scan */
#define AWI_DRV_ADHSY 0x3 /* adhoc synced */
#define AWI_DRV_INFSC 0x4 /* inf scanning */
#define AWI_DRV_INFAUTH 0x5 /* inf authed */
#define AWI_DRV_INFASSOC 0x6 /* inf associated */
#define AWI_DRV_INFTOSS 0x7 /* inf handoff */
#define AWI_DRV_APNONE 0x8 /* AP activity: no assoc */
#define AWI_DRV_APQUIET 0xc /* AP: >=one assoc, no traffic */
#define AWI_DRV_APLO 0xd /* AP: >=one assoc, light tfc */
#define AWI_DRV_APMED 0xe /* AP: >=one assoc, mod tfc */
#define AWI_DRV_APHIGH 0xf /* AP: >=one assoc, heavy tfc */
#define AWI_DRV_AUTORXLED 0x10
#define AWI_DRV_AUTOTXLED 0x20
#define AWI_DRV_RXLED 0x40
#define AWI_DRV_TXLED 0x80
#define AWI_VBM_OFFSET 0x500 /* Virtual Bit Map */
#define AWI_VBM_LENGTH 0x501
#define AWI_VBM_BITMAP 0x502
#define AWI_BUFFERS 0x600 /* Buffers */
#define AWI_BUFFERS_END 0x6000
/*
* Receive descriptors; there are a linked list of these chained
* through the "NEXT" fields, starting from XXX
*/
#define AWI_RXD_SIZE 0x18
#define AWI_RXD_NEXT 0x4
#define AWI_RXD_NEXT_LAST 0x80000000
#define AWI_RXD_HOST_DESC_STATE 0x9
#define AWI_RXD_ST_OWN 0x80 /* host owns this */
#define AWI_RXD_ST_CONSUMED 0x40 /* host is done */
#define AWI_RXD_ST_LF 0x20 /* last frag */
#define AWI_RXD_ST_CRC 0x08 /* CRC error */
#define AWI_RXD_ST_OFLO 0x02 /* possible buffer overrun */
#define AWI_RXD_ST_RXERROR 0x01 /* this frame is borked; discard me */
#define AWI_RXD_RSSI 0xa /* 1 byte: radio strength indicator */
#define AWI_RXD_INDEX 0xb /* 1 byte: FH hop index or DS channel */
#define AWI_RXD_LOCALTIME 0xc /* 4 bytes: local time of RX */
#define AWI_RXD_START_FRAME 0x10 /* 4 bytes: ptr to first received byte */
#define AWI_RXD_LEN 0x14 /* 2 bytes: rx len in bytes */
#define AWI_RXD_RATE 0x16 /* 1 byte: rx rate in 1e5 bps */
/*
* Transmit descriptors.
*/
#define AWI_TXD_SIZE 0x18
#define AWI_TXD_START 0x00 /* pointer to start of frame */
#define AWI_TXD_NEXT 0x04 /* pointer to next TXD */
#define AWI_TXD_LENGTH 0x08 /* length of frame */
#define AWI_TXD_STATE 0x0a /* state */
#define AWI_TXD_ST_OWN 0x80 /* MAC owns this */
#define AWI_TXD_ST_DONE 0x40 /* MAC is done */
#define AWI_TXD_ST_REJ 0x20 /* MAC doesn't like */
#define AWI_TXD_ST_MSDU 0x10 /* MSDU timeout */
#define AWI_TXD_ST_ABRT 0x08 /* TX aborted */
#define AWI_TXD_ST_RETURNED 0x04 /* TX returned */
#define AWI_TXD_ST_RETRY 0x02 /* TX retries exceeded */
#define AWI_TXD_ST_ERROR 0x01 /* TX error */
#define AWI_TXD_RATE 0x0b /* rate */
#define AWI_RATE_1MBIT 10
#define AWI_RATE_2MBIT 20
#define AWI_TXD_NDA 0x0c /* num DIFS attempts */
#define AWI_TXD_NDF 0x0d /* num DIFS failures */
#define AWI_TXD_NSA 0x0e /* num SIFS attempts */
#define AWI_TXD_NSF 0x0f /* num SIFS failures */
#define AWI_TXD_NRA 0x14 /* num RTS attempts */
#define AWI_TXD_NDTA 0x15 /* num data attempts */
#define AWI_TXD_CTL 0x16 /* control */
#define AWI_TXD_CTL_PSN 0x80 /* preserve sequence in MAC frame */
#define AWI_TXD_CTL_BURST 0x02 /* host is doing 802.11 fragmt. */
#define AWI_TXD_CTL_FRAGS 0x01 /* override normal fragmentation */
/*
* MIB structures.
*/
#define AWI_ESS_ID_SIZE (IEEE80211_NWID_LEN+2)
struct awi_mib_local {
u_int8_t Fragmentation_Dis;
u_int8_t Add_PLCP_Dis;
u_int8_t MAC_Hdr_Prsv;
u_int8_t Rx_Mgmt_Que_En;
u_int8_t Re_Assembly_Dis;
u_int8_t Strip_PLCP_Dis;
u_int8_t Rx_Error_Dis;
u_int8_t Power_Saving_Mode_Dis;
u_int8_t Accept_All_Multicast_Dis;
u_int8_t Check_Seq_Cntl_Dis;
u_int8_t Flush_CFP_Queue_On_CF_End;
u_int8_t Network_Mode;
u_int8_t PWD_Lvl;
u_int8_t CFP_Mode;
u_int8_t Tx_Buffer_Offset[4];
u_int8_t Tx_Buffer_Size[4];
u_int8_t Rx_Buffer_Offset[4];
u_int8_t Rx_Buffer_Size[4];
u_int8_t Acting_as_AP;
u_int8_t Fill_CFP;
} __attribute__((__packed__));
struct awi_mib_mac {
u_int8_t _Reserved1[2];
u_int8_t _Reserved2[2];
u_int8_t aRTS_Threshold[2];
u_int8_t aCW_max[2];
u_int8_t aCW_min[2];
u_int8_t aPromiscuous_Enable;
u_int8_t _Reserved3;
u_int8_t _Reserved4[4];
u_int8_t aShort_Retry_Limit;
u_int8_t aLong_Retry_Limit;
u_int8_t aMax_Frame_Length[2];
u_int8_t aFragmentation_Threshold[2];
u_int8_t aProbe_Delay[2];
u_int8_t aMin_Probe_Response_Time[2];
u_int8_t aMax_Probe_Response_Time[2];
u_int8_t aMax_Transmit_MSDU_Lifetime[4];
u_int8_t aMax_Receive_MSDU_Lifetime[4];
u_int8_t aStation_Basic_Rate[2];
u_int8_t aDesired_ESS_ID[AWI_ESS_ID_SIZE];
} __attribute__((__packed__));
struct awi_mib_stat {
u_int8_t aTransmitted_MPDU_Count[4];
u_int8_t aTransmitted_MSDU_Count[4];
u_int8_t aOctets_Transmitted_Cnt[4];
u_int8_t aMulticast_Transmitted_Frame_Count[2];
u_int8_t aBroadcast_Transmitted_Frame_Count[2];
u_int8_t aFailed_Count[4];
u_int8_t aRetry_Count[4];
u_int8_t aMultiple_Retry_Count[4];
u_int8_t aFrame_Duplicate_Count[4];
u_int8_t aRTS_Success_Count[4];
u_int8_t aRTS_Failure_Count[4];
u_int8_t aACK_Failure_Count[4];
u_int8_t aReceived_Frame_Count [4];
u_int8_t aOctets_Received_Count[4];
u_int8_t aMulticast_Received_Count[2];
u_int8_t aBroadcast_Received_Count[2];
u_int8_t aFCS_Error_Count[4];
u_int8_t aError_Count[4];
u_int8_t aWEP_Undecryptable_Count[4];
} __attribute__((__packed__));
struct awi_mib_mgt {
u_int8_t aPower_Mgt_Mode;
u_int8_t aScan_Mode;
#define AWI_SCAN_PASSIVE 0x00
#define AWI_SCAN_ACTIVE 0x01
#define AWI_SCAN_BACKGROUND 0x02
u_int8_t aScan_State;
u_int8_t aDTIM_Period;
u_int8_t aATIM_Window[2];
u_int8_t Wep_Required;
#define AWI_WEP_ON 0x10
#define AWI_WEP_OFF 0x00
u_int8_t _Reserved1;
u_int8_t aBeacon_Period[2];
u_int8_t aPassive_Scan_Duration[2];
u_int8_t aListen_Interval[2];
u_int8_t aMedium_Occupancy_Limit[2];
u_int8_t aMax_MPDU_Time[2];
u_int8_t aCFP_Max_Duration[2];
u_int8_t aCFP_Rate;
u_int8_t Do_Not_Receive_DTIMs;
u_int8_t aStation_ID[2];
u_int8_t aCurrent_BSS_ID[ETHER_ADDR_LEN];
u_int8_t aCurrent_ESS_ID[AWI_ESS_ID_SIZE];
} __attribute__((__packed__));
#define AWI_GROUP_ADDR_SIZE 4
struct awi_mib_addr {
u_int8_t aMAC_Address[ETHER_ADDR_LEN];
u_int8_t aGroup_Addresses[AWI_GROUP_ADDR_SIZE][ETHER_ADDR_LEN];
u_int8_t aTransmit_Enable_Status;
u_int8_t _Reserved1;
} __attribute__((__packed__));
#define AWI_PWR_LEVEL_SIZE 4
struct awi_mib_phy {
u_int8_t aSlot_Time[2];
u_int8_t aSIFS[2];
u_int8_t aMPDU_Maximum[2];
u_int8_t aHop_Time[2];
u_int8_t aSuprt_Data_Rates[4];
u_int8_t aCurrent_Reg_Domain;
#define AWI_REG_DOMAIN_US 0x10
#define AWI_REG_DOMAIN_CA 0x20
#define AWI_REG_DOMAIN_EU 0x30
#define AWI_REG_DOMAIN_ES 0x31
#define AWI_REG_DOMAIN_FR 0x32
#define AWI_REG_DOMAIN_JP 0x40
u_int8_t aPreamble_Lngth;
u_int8_t aPLCP_Hdr_Lngth;
u_int8_t Pwr_Up_Time[AWI_PWR_LEVEL_SIZE][2];
u_int8_t IEEE_PHY_Type;
#define AWI_PHY_TYPE_FH 1
#define AWI_PHY_TYPE_DS 2
#define AWI_PHY_TYPE_IR 3
u_int8_t RCR_33A_Bits[8];
} __attribute__((__packed__));
#endif /* _DEV_IC_AWIREG_H */

161
sys/dev/awi/awivar.h
View File

@ -1,161 +0,0 @@
/* $NetBSD: awivar.h,v 1.20 2004/01/15 09:39:15 onoe Exp $ */
/* $FreeBSD$ */
/*-
* Copyright (c) 1999,2000,2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Bill Sommerfeld
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _DEV_IC_AWIVAR_H
#define _DEV_IC_AWIVAR_H
/* timer values in msec */
#define AWI_SELFTEST_TIMEOUT 5000
#define AWI_CMD_TIMEOUT 2000
#define AWI_LOCKOUT_TIMEOUT 50
#define AWI_ASCAN_DURATION 100
#define AWI_ASCAN_WAIT 3000
#define AWI_PSCAN_DURATION 200
#define AWI_PSCAN_WAIT 5000
#define AWI_TRANS_TIMEOUT 5000
#define AWI_NTXBUFS 4
enum awi_sub_state {
AWI_ST_NONE,
AWI_ST_SCAN_INIT,
AWI_ST_SCAN_SETMIB,
AWI_ST_SCAN_SCCMD,
AWI_ST_SUB_INIT,
AWI_ST_SUB_SETSS,
AWI_ST_SUB_SYNC
};
#define AWI_WAIT 0 /* must wait for completion */
#define AWI_NOWAIT 1 /* do not wait */
struct awi_chanset {
u_int8_t cs_type;
u_int8_t cs_region;
u_int8_t cs_min;
u_int8_t cs_max;
u_int8_t cs_def;
};
struct awi_softc {
#ifdef __NetBSD__
struct device sc_dev;
void (*sc_power)(struct awi_softc *, int);
#endif
#ifdef __FreeBSD__
struct arpcom sc_arp;
device_t sc_dev;
#endif
struct am79c930_softc sc_chip;
struct ieee80211com sc_ic;
u_char sc_banner[AWI_BANNER_LEN];
int (*sc_enable)(struct awi_softc *);
void (*sc_disable)(struct awi_softc *);
int (*sc_newstate)(struct ieee80211com *,
enum ieee80211_state, int);
void (*sc_recv_mgmt)(struct ieee80211com *,
struct mbuf *, struct ieee80211_node *,
int, int, int, u_int32_t);
int (*sc_send_mgmt)(struct ieee80211com *,
struct ieee80211_node *, int, int);
void *sc_sdhook; /* shutdown hook */
void *sc_powerhook; /* power management hook */
unsigned int sc_attached:1,
sc_enabled:1,
sc_busy:1,
sc_cansleep:1,
sc_enab_intr:1,
sc_adhoc_ap:1,
sc_invalid:1;
enum ieee80211_state sc_nstate;
enum awi_sub_state sc_substate;
int sc_sleep_cnt;
u_int8_t sc_cmd_inprog;
u_int8_t sc_cur_chan;
int sc_rx_timer;
u_int32_t sc_rxdoff;
u_int32_t sc_rxmoff;
struct mbuf *sc_rxpend;
int sc_tx_timer;
u_int32_t sc_txbase;
u_int32_t sc_txend;
u_int32_t sc_txnext;
u_int32_t sc_txdone;
struct awi_mib_local sc_mib_local;
struct awi_mib_addr sc_mib_addr;
struct awi_mib_mac sc_mib_mac;
struct awi_mib_stat sc_mib_stat;
struct awi_mib_mgt sc_mib_mgt;
struct awi_mib_phy sc_mib_phy;
};
#define awi_read_1(sc, off) ((sc)->sc_chip.sc_ops->read_1)(&sc->sc_chip, off)
#define awi_read_2(sc, off) ((sc)->sc_chip.sc_ops->read_2)(&sc->sc_chip, off)
#define awi_read_4(sc, off) ((sc)->sc_chip.sc_ops->read_4)(&sc->sc_chip, off)
#define awi_read_bytes(sc, off, ptr, len) \
((sc)->sc_chip.sc_ops->read_bytes)(&sc->sc_chip, off, ptr, len)
#define awi_write_1(sc, off, val) \
((sc)->sc_chip.sc_ops->write_1)(&sc->sc_chip, off, val)
#define awi_write_2(sc, off, val) \
((sc)->sc_chip.sc_ops->write_2)(&sc->sc_chip, off, val)
#define awi_write_4(sc, off, val) \
((sc)->sc_chip.sc_ops->write_4)(&sc->sc_chip, off, val)
#define awi_write_bytes(sc, off, ptr, len) \
((sc)->sc_chip.sc_ops->write_bytes)(&sc->sc_chip, off, ptr, len)
#define awi_drvstate(sc, state) \
awi_write_1(sc, AWI_DRIVERSTATE, \
((state) | AWI_DRV_AUTORXLED|AWI_DRV_AUTOTXLED))
int awi_attach(struct awi_softc *);
int awi_detach(struct awi_softc *);
#ifdef __NetBSD__
int awi_activate(struct device *, enum devact);
void awi_power(int, void *);
#endif
void awi_shutdown(void *);
int awi_intr(void *);
#endif /* _DEV_IC_AWIVAR_H */

283
sys/dev/awi/if_awi_pccard.c
View File

@ -1,283 +0,0 @@
/*-
* Copyright (c) 2000 Atsushi Onoe <onoe@sm.sony.co.jp>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/if_media.h>
#include <net/ethernet.h>
#include <net80211/ieee80211_var.h>
#include <dev/awi/am79c930reg.h>
#include <dev/awi/am79c930var.h>
#include <dev/awi/awireg.h>
#include <dev/awi/awivar.h>
#include <dev/pccard/pccardvar.h>
#include "card_if.h"
#include "pccarddevs.h"
struct awi_pccard_softc {
struct awi_softc sc_awi;
u_int8_t sc_version[AWI_BANNER_LEN];
int sc_intr_mask;
void *sc_intrhand;
struct resource *sc_irq_res;
int sc_irq_rid;
struct resource *sc_port_res;
int sc_port_rid;
struct resource *sc_mem_res;
int sc_mem_rid;
};
static const struct pccard_product awi_pccard_products[] = {
PCMCIA_CARD(AMD, AM79C930),
PCMCIA_CARD(BAY, STACK_650),
PCMCIA_CARD(BAY, STACK_660),
PCMCIA_CARD(BAY, SURFER_PRO),
PCMCIA_CARD(ICOM, SL200),
PCMCIA_CARD(NOKIA, C020_WLAN),
PCMCIA_CARD(FARALLON, SKYLINE),
PCMCIA_CARD(ZOOM, AIR_4000),
{ NULL }
};
static int awi_pccard_probe(device_t);
static int awi_pccard_attach(device_t);
static int awi_pccard_detach(device_t);
static void awi_pccard_shutdown(device_t);
static int awi_pccard_enable(struct awi_softc *);
static void awi_pccard_disable(struct awi_softc *);
static int
awi_pccard_probe(device_t dev)
{
const struct pccard_product *pp;
if ((pp = pccard_product_lookup(dev, awi_pccard_products,
sizeof(awi_pccard_products[0]), NULL)) != NULL) {
if (pp->pp_name != NULL)
device_set_desc(dev, pp->pp_name);
return 0;
}
return ENXIO;
}
/*
* Initialize the device - called from Slot manager.
*/
static int
awi_pccard_attach(device_t dev)
{
struct awi_pccard_softc *psc = device_get_softc(dev);
struct awi_softc *sc = &psc->sc_awi;
int error = 0;
psc->sc_port_rid = 0;
psc->sc_port_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
&psc->sc_port_rid, 0, ~0, AM79C930_IO_SIZE,
rman_make_alignment_flags(AM79C930_IO_ALIGN) | RF_ACTIVE);
if (!psc->sc_port_res)
return ENOMEM;
sc->sc_chip.sc_iot = rman_get_bustag(psc->sc_port_res);
sc->sc_chip.sc_ioh = rman_get_bushandle(psc->sc_port_res);
am79c930_chip_init(&sc->sc_chip, 0);
tsleep(sc, PWAIT, "awiprb", 1);
awi_read_bytes(sc, AWI_BANNER, psc->sc_version, AWI_BANNER_LEN);
if (memcmp(psc->sc_version, "PCnetMobile:", 12) != 0) {
device_printf(dev, "awi_pccard_probe: bad banner: %12D\n",
psc->sc_version, " ");
error = ENXIO;
} else
device_set_desc(dev, psc->sc_version);
psc->sc_irq_res = 0;
psc->sc_mem_res = 0;
psc->sc_intrhand = 0;
psc->sc_port_rid = 0;
psc->sc_port_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
&psc->sc_port_rid, 0, ~0, 16, RF_ACTIVE);
if (!psc->sc_port_res) {
device_printf(dev, "awi_pccard_attach: port alloc failed\n");
goto fail;
}
sc->sc_chip.sc_iot = rman_get_bustag(psc->sc_port_res);
sc->sc_chip.sc_ioh = rman_get_bushandle(psc->sc_port_res);
psc->sc_irq_rid = 0;
psc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&psc->sc_irq_rid, RF_ACTIVE);
if (!psc->sc_irq_res) {
device_printf(dev, "awi_pccard_attach: irq alloc failed\n");
goto fail;
}
psc->sc_mem_rid = 0;
#if 1
/*
* XXX: awi needs to access memory with 8bit,
* but OLDCARD apparently maps memory with MDF_16BITS flag.
* So memory mapped access is disabled and use IO port instead.
* XXX: Should check to see if this is true of NEWCARD
*/
psc->sc_mem_res = 0;
#else
psc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
&psc->sc_mem_rid, 0, ~0, 0x8000, RF_ACTIVE);
#endif
if (psc->sc_mem_res) {
sc->sc_chip.sc_memt = rman_get_bustag(psc->sc_mem_res);
sc->sc_chip.sc_memh = rman_get_bushandle(psc->sc_mem_res);
am79c930_chip_init(&sc->sc_chip, 1);
} else
am79c930_chip_init(&sc->sc_chip, 0);
sc->sc_dev = dev;
sc->sc_cansleep = 1;
sc->sc_enable = awi_pccard_enable;
sc->sc_disable = awi_pccard_disable;
if (awi_pccard_enable(sc))
goto fail;
sc->sc_enabled = 1;
error = awi_attach(sc);
sc->sc_enabled = 0; /*XXX*/
awi_pccard_disable(sc);
if (error == 0)
return 0;
device_printf(dev, "awi_pccard_attach: awi_attach failed\n");
fail:
awi_pccard_detach(dev);
if (error == 0)
error = ENXIO;
return error;
}
static int
awi_pccard_detach(device_t dev)
{
struct awi_pccard_softc *psc = device_get_softc(dev);
struct awi_softc *sc = &psc->sc_awi;
awi_detach(sc);
if (psc->sc_mem_res) {
bus_release_resource(dev, SYS_RES_MEMORY, psc->sc_mem_rid,
psc->sc_mem_res);
psc->sc_mem_res = 0;
}
if (psc->sc_irq_res) {
bus_release_resource(dev, SYS_RES_IRQ, psc->sc_irq_rid,
psc->sc_irq_res);
psc->sc_irq_res = 0;
}
if (psc->sc_port_res) {
bus_release_resource(dev, SYS_RES_IOPORT, psc->sc_port_rid,
psc->sc_port_res);
psc->sc_port_res = 0;
}
return 0;
}
static void
awi_pccard_shutdown(device_t dev)
{
struct awi_pccard_softc *psc = device_get_softc(dev);
struct awi_softc *sc = &psc->sc_awi;
awi_shutdown(sc);
}
static int
awi_pccard_enable(struct awi_softc *sc)
{
device_t dev = sc->sc_dev;
struct awi_pccard_softc *psc = device_get_softc(dev);
int error;
if (psc->sc_intrhand == 0) {
error = bus_setup_intr(dev, psc->sc_irq_res, INTR_TYPE_NET,
NULL, (void (*)(void *))awi_intr, sc, &psc->sc_intrhand);
if (error) {
device_printf(dev,
"couldn't establish interrupt error=%d\n", error);
return error;
}
}
return 0;
}
static void
awi_pccard_disable(struct awi_softc *sc)
{
device_t dev = sc->sc_dev;
struct awi_pccard_softc *psc = device_get_softc(dev);
if (psc->sc_intrhand) {
bus_teardown_intr(dev, psc->sc_irq_res, psc->sc_intrhand);
psc->sc_intrhand = 0;
}
}
static device_method_t awi_pccard_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, awi_pccard_probe),
DEVMETHOD(device_attach, awi_pccard_attach),
DEVMETHOD(device_detach, awi_pccard_detach),
DEVMETHOD(device_shutdown, awi_pccard_shutdown),
{ 0, 0 }
};
static driver_t awi_pccard_driver = {
"awi",
awi_pccard_methods,
sizeof(struct awi_pccard_softc),
};
extern devclass_t awi_devclass;
DRIVER_MODULE(awi, pccard, awi_pccard_driver, awi_devclass, 0, 0);
MODULE_DEPEND(awi, wlan, 1, 1, 1);

1
sys/i386/conf/GENERIC
View File

@ -259,7 +259,6 @@ device an # Aironet 4500/4800 802.11 wireless NICs.
device ath # Atheros pci/cardbus NIC's
device ath_hal # Atheros HAL (Hardware Access Layer)
device ath_rate_sample # SampleRate tx rate control for ath
device awi # BayStack 660 and others
device ral # Ralink Technology RT2500 wireless NICs.
device wi # WaveLAN/Intersil/Symbol 802.11 wireless NICs.
#device wl # Older non 802.11 Wavelan wireless NIC.

1
sys/i386/conf/PAE
View File

@ -80,6 +80,5 @@ nodevice an
nodevice ath # Atheros pci/cardbus NIC's
nodevice ath_hal # Atheros HAL (Hardware Access Layer)
nodevice ath_rate_sample # SampleRate tx rate control for ath
nodevice awi
nodevice ral
nodevice wi

2
sys/modules/Makefile
View File

@ -33,7 +33,6 @@ SUBDIR= ${_3dfx} \
${_ath_rate_sample} \
aue \
${_auxio} \
${_awi} \
axe \
bce \
bfe \
@ -377,7 +376,6 @@ _ath_hal= ath_hal
_ath_rate_amrr= ath_rate_amrr
_ath_rate_onoe= ath_rate_onoe
_ath_rate_sample=ath_rate_sample
_awi= awi
_bktr= bktr
_cardbus= cardbus
_cbb= cbb

14
sys/modules/awi/Makefile
View File

@ -1,14 +0,0 @@
# $FreeBSD$
.PATH: ${.CURDIR}/../../dev/awi
KMOD= if_awi
SRCS= am79c930.c awi.c if_awi_pccard.c
SRCS+= bus_if.h card_if.h device_if.h opt_inet.h pccarddevs.h
.if !defined(KERNBUILDDIR)
opt_inet.h:
echo "#define INET 1" > opt_inet.h
.endif
.include <bsd.kmod.mk>

1
sys/pc98/conf/GENERIC
View File

@ -221,7 +221,6 @@ device an # Aironet 4500/4800 802.11 wireless NICs.
device ath # Atheros pci/cardbus NIC's
device ath_hal # Atheros HAL (Hardware Access Layer)
device ath_rate_sample # SampleRate tx rate control for ath
device awi # BayStack 660 and others
device ral # Ralink Technology RT2500 wireless NICs.
device wi # WaveLAN/Intersil/Symbol 802.11 wireless NICs.
#device wl # Older non 802.11 Wavelan wireless NIC.