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Reserve numbers for XScale.

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Reviewed by:	jkoshy
This commit is contained in:
Rui Paulo 2009-10-02 11:14:12 +00:00
parent f143a35bf1
commit f49e371d3b
1 changed files with 6 additions and 4 deletions
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10
sys/sys/pmc.h
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@ -84,7 +84,8 @@
__PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \
__PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \
__PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \
__PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7")
__PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \
__PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale")
enum pmc_cputype {
#undef __PMC_CPU
@ -93,7 +94,7 @@ enum pmc_cputype {
};
#define PMC_CPU_FIRST PMC_CPU_AMD_K7
#define PMC_CPU_LAST PMC_CPU_INTEL_COREI7
#define PMC_CPU_LAST PMC_CPU_INTEL_XSCALE
/*
* Classes of PMCs
@ -107,7 +108,8 @@ enum pmc_cputype {
__PMC_CLASS(P6) /* Intel Pentium Pro counters */ \
__PMC_CLASS(P4) /* Intel Pentium-IV counters */ \
__PMC_CLASS(IAF) /* Intel Core2/Atom, fixed function */ \
__PMC_CLASS(IAP) /* Intel Core...Atom, programmable */
__PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \
__PMC_CLASS(XSCALE) /* Intel XScale counters */
enum pmc_class {
#undef __PMC_CLASS
@ -116,7 +118,7 @@ enum pmc_class {
};
#define PMC_CLASS_FIRST PMC_CLASS_TSC
#define PMC_CLASS_LAST PMC_CLASS_IAP
#define PMC_CLASS_LAST PMC_CLASS_XSCALE
/*
* A PMC can be in the following states: