Fix a panic brought about by writing an MSR without a proper mask.
All of the necessary wrmsr calls are now preceded by a rdmsr and we leave the reserved bits alone. Document the bits in the relevant registers for future reference. Tested by: mdf MFC after: 1 week
This commit is contained in:
George V. Neville-Neil
parent
797ab05ef6
commit
f4a9c30419
@ -147,6 +147,7 @@ core_pcpu_fini(struct pmc_mdep *md, int cpu)
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int core_ri, n, npmc;
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struct pmc_cpu *pc;
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struct core_cpu *cc;
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uint64_t msr = 0;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[core,%d] insane cpu number (%d)", __LINE__, cpu));
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@ -166,11 +167,14 @@ core_pcpu_fini(struct pmc_mdep *md, int cpu)
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npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
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core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
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for (n = 0; n < npmc; n++)
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wrmsr(IAP_EVSEL0 + n, 0);
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for (n = 0; n < npmc; n++) {
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msr = rdmsr(IAP_EVSEL0 + n);
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wrmsr(IAP_EVSEL0 + n, msr & ~IAP_EVSEL_MASK);
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}
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if (core_cputype != PMC_CPU_INTEL_CORE) {
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wrmsr(IAF_CTRL, 0);
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msr = rdmsr(IAF_CTRL);
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wrmsr(IAF_CTRL, msr & ~IAF_CTRL_MASK);
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npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
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}
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@ -374,6 +378,7 @@ iaf_start_pmc(int cpu, int ri)
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{
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struct pmc *pm;
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struct core_cpu *iafc;
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uint64_t msr = 0;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[core,%d] illegal CPU value %d", __LINE__, cpu));
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@ -387,12 +392,15 @@ iaf_start_pmc(int cpu, int ri)
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iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
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wrmsr(IAF_CTRL, iafc->pc_iafctrl);
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msr = rdmsr(IAF_CTRL);
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wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
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do {
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iafc->pc_resync = 0;
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iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
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wrmsr(IA_GLOBAL_CTRL, iafc->pc_globalctrl);
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msr = rdmsr(IA_GLOBAL_CTRL);
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wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
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IAF_GLOBAL_CTRL_MASK));
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} while (iafc->pc_resync != 0);
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PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
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@ -407,6 +415,7 @@ iaf_stop_pmc(int cpu, int ri)
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{
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uint32_t fc;
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struct core_cpu *iafc;
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uint64_t msr = 0;
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PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
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@ -425,12 +434,15 @@ iaf_stop_pmc(int cpu, int ri)
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iafc->pc_iafctrl &= ~fc;
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PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
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wrmsr(IAF_CTRL, iafc->pc_iafctrl);
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msr = rdmsr(IAF_CTRL);
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wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
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do {
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iafc->pc_resync = 0;
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iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
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wrmsr(IA_GLOBAL_CTRL, iafc->pc_globalctrl);
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msr = rdmsr(IA_GLOBAL_CTRL);
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wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
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IAF_GLOBAL_CTRL_MASK));
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} while (iafc->pc_resync != 0);
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PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
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@ -445,6 +457,7 @@ iaf_write_pmc(int cpu, int ri, pmc_value_t v)
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{
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struct core_cpu *cc;
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struct pmc *pm;
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uint64_t msr;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[core,%d] illegal cpu value %d", __LINE__, cpu));
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@ -460,9 +473,11 @@ iaf_write_pmc(int cpu, int ri, pmc_value_t v)
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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v = iaf_reload_count_to_perfctr_value(v);
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wrmsr(IAF_CTRL, 0); /* Turn off fixed counters */
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wrmsr(IAF_CTR0 + ri, v);
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wrmsr(IAF_CTRL, cc->pc_iafctrl);
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msr = rdmsr(IAF_CTRL);
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wrmsr(IAF_CTRL, msr & ~IAF_CTRL_MASK);
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wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
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msr = rdmsr(IAF_CTRL);
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wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
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PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
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"pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
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@ -1879,6 +1894,7 @@ iap_stop_pmc(int cpu, int ri)
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{
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struct pmc *pm;
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struct core_cpu *cc;
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uint64_t msr;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[core,%d] illegal cpu value %d", __LINE__, cpu));
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@ -1894,7 +1910,8 @@ iap_stop_pmc(int cpu, int ri)
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PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
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wrmsr(IAP_EVSEL0 + ri, 0); /* stop hw */
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msr = rdmsr(IAP_EVSEL0 + ri);
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wrmsr(IAP_EVSEL0 + ri, msr & IAP_EVSEL_MASK); /* stop hw */
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if (core_cputype == PMC_CPU_INTEL_CORE)
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return (0);
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@ -1937,7 +1954,7 @@ iap_write_pmc(int cpu, int ri, pmc_value_t v)
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* a stopped state when the pcd_write() entry point is called.
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*/
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wrmsr(IAP_PMC0 + ri, v);
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wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1));
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return (0);
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}
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@ -1987,6 +2004,7 @@ core_intr(int cpu, struct trapframe *tf)
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struct pmc *pm;
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struct core_cpu *cc;
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int error, found_interrupt, ri;
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uint64_t msr = 0;
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PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
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TRAPF_USERMODE(tf));
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@ -2018,7 +2036,8 @@ core_intr(int cpu, struct trapframe *tf)
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* Stop the counter, reload it but only restart it if
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* the PMC is not stalled.
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*/
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wrmsr(IAP_EVSEL0 + ri, 0);
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msr = rdmsr(IAP_EVSEL0 + ri);
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wrmsr(IAP_EVSEL0 + ri, msr & ~IAP_EVSEL_MASK);
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wrmsr(IAP_PMC0 + ri, v);
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if (error)
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@ -67,20 +67,59 @@ struct pmc_md_iap_op_pmcallocate {
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/*
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* Fixed-function counters.
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*/
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#define IAF_MASK 0xF
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#define IAF_COUNTER_MASK 0x0000ffffffffffff
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#define IAF_CTR0 0x309
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#define IAF_CTR1 0x30A
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#define IAF_CTR2 0x30B
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/*
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* The IAF_CTRL MSR is laid out in the following way.
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*
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* Bit Position Use
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* 63 - 12 Reserved (do not touch)
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* 11 Ctr 2 PMI
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* 10 Reserved (do not touch)
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* 9-8 Ctr 2 Enable
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* 7 Ctr 1 PMI
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* 6 Reserved (do not touch)
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* 5-4 Ctr 1 Enable
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* 3 Ctr 0 PMI
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* 2 Reserved (do not touch)
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* 1-0 Ctr 0 Enable (3: All Levels, 2: User, 1: OS, 0: Disable)
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*/
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#define IAF_OFFSET 32
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#define IAF_CTRL 0x38D
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#define IAF_CTRL_MASK 0x0000000000000bbb
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/*
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* Programmable counters.
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*/
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#define IAP_PMC0 0x0C1
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/*
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* IAP_EVSEL(n) is laid out in the following way.
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*
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* Bit Position Use
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* 63-31 Reserved (do not touch)
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* 31-24 Counter Mask
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* 23 Invert
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* 22 Enable
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* 21 Reserved (do not touch)
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* 20 APIC Interrupt Enable
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* 19 Pin Control
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* 18 Edge Detect
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* 17 OS
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* 16 User
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* 15-8 Unit Mask
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* 7-0 Event Select
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*/
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#define IAP_EVSEL_MASK 0x00000000ffdfffff
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#define IAP_EVSEL0 0x186
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/*
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@ -90,6 +129,21 @@ struct pmc_md_iap_op_pmcallocate {
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#define IA_GLOBAL_STATUS 0x38E
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#define IA_GLOBAL_CTRL 0x38F
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/*
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* IA_GLOBAL_CTRL is layed out in the following way.
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*
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* Bit Position Use
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* 63-35 Reserved (do not touch)
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* 34 IAF Counter 2 Enable
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* 33 IAF Counter 1 Enable
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* 32 IAF Counter 0 Enable
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* 31-0 Depends on programmable counters
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*/
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/* The mask is only for the fixed porttion of the register. */
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#define IAF_GLOBAL_CTRL_MASK 0x0000000700000000
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#define IA_GLOBAL_OVF_CTRL 0x390
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#define IA_GLOBAL_STATUS_FLAG_CONDCHG (1ULL << 63)
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