Merge diff between rev 1.08 and rev 1.11 of Tekram driver, this notably add
support for Tekram DC395U2W cards. Add a fix submitted by joerg@ to correctly report some errors to CAM. Use bus_dma instead of the remaining vtophys().
This commit is contained in:
Olivier Houchard
parent
ec73437395
commit
f5ca18bc8c
1002
sys/dev/trm/trm.c
1002
sys/dev/trm/trm.c
File diff suppressed because it is too large
Load Diff
@ -75,8 +75,8 @@ struct trm_target_info {
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/*;----------------------Segment Entry------------------------------------*/
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typedef struct _SGentry {
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u_long address;
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u_long length;
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u_int32_t address;
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u_int32_t length;
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} SGentry, *PSEG;
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/*
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*-----------------------------------------------------------------------
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@ -84,14 +84,14 @@ typedef struct _SGentry {
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*-----------------------------------------------------------------------
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*/
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#define MAX_ADAPTER_NUM 4
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#define MAX_DEVICES 16
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#define MAX_SG_LISTENTRY 32
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#define MAX_TARGETS 16
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#define MAX_TAGS_CMD_QUEUE 32 /* MAX_CMD_QUEUE 20*/
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#define MAX_CMD_PER_LUN 32
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#define MAX_SRB_CNT MAX_CMD_PER_LUN*4
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#define MAX_START_JOB MAX_CMD_PER_LUN*4
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#define TRM_MAX_ADAPTER_NUM 4
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#define TRM_MAX_DEVICES 16
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#define TRM_MAX_SG_LISTENTRY 32
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#define TRM_MAX_TARGETS 16
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#define TRM_MAX_TAGS_CMD_QUEUE 256 /* MAX_CMD_QUEUE 20*/
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#define TRM_MAX_CMD_PER_LUN 32
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#define TRM_MAX_SRB_CNT 256
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#define TRM_MAX_START_JOB 256
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#define TRM_NSEG (btoc(MAXPHYS) + 1)
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#define TRM_MAXTRANSFER_SIZE 0xFFFFFF /* restricted by 24 bit counter */
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#define PAGELEN 4096
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@ -142,19 +142,23 @@ struct _SRB {
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u_int8_t CmdBlock[12];
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u_long Segment0[2];
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u_long Segment1[2];
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u_long PhysSRB;
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struct _SRB *pNextSRB;
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struct _DCB *pSRBDCB;
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SGentry SegmentX[MAX_SG_LISTENTRY];
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SGentry SgSenseTemp;
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PSEG pSRBSGL; /* scatter gather list */
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u_int32_t SRBSGPhyAddr; /* a segment starting address */
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u_int32_t SRBTotalXferLength;
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/*
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* CAM ccb
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*/
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union ccb *pccb;
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union ccb *pccb;
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bus_dma_tag_t parent_dmat;
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bus_dma_tag_t sg_dmat;
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bus_dmamap_t sg_dmamap;
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bus_dmamap_t dmamap;
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PSEG SRBSGListPointer; /* scatter gather list */
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u_long SRBTotalXferLength;
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u_long SRBSGPhyAddr; /* a segment starting address */
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u_int16_t SRBState;
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u_int8_t * pMsgPtr;
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@ -170,8 +174,6 @@ struct _SRB {
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u_int8_t SRBStatus;
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u_int8_t RetryCnt;
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/* b0-AutoReqSense,b6-Read,b7-write */
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/* b4-settimeout,b5-Residual valid */
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u_int8_t SRBFlag;
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u_int8_t ScsiCmdLen;
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u_int8_t ScsiPhase;
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@ -186,25 +188,19 @@ typedef struct _SRB TRM_SRB, *PSRB;
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*/
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struct _DCB
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{
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struct _DCB *pNextDCB;
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struct _ACB *pDCBACB;
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PSRB pWaitingSRB;
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PSRB pWaitLastSRB;
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PSRB pWaitingLastSRB;
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PSRB pGoingSRB;
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PSRB pGoingLastSRB;
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PSRB pActiveSRB;
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PSRB RevSRB;
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u_long TagMask;
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u_int16_t GoingSRBCnt;
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u_int16_t WaitSRBCnt;
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u_int16_t MaxActiveCommandCnt;
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u_int8_t TargetID; /*; SCSI Target ID (SCSI Only) */
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u_int8_t TargetLUN; /*; SCSI Log. Unit (SCSI Only) */
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u_int8_t TargetID; /*; SCSI Target ID (SCSI Only) */
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u_int8_t TargetLUN; /*; SCSI Log. Unit (SCSI Only) */
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u_int8_t DCBFlag;
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u_int8_t DevType;
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@ -213,14 +209,14 @@ struct _DCB
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u_int8_t SyncPeriod; /* for reg. */
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u_int8_t SyncOffset; /* for reg. and nego.(low nibble) */
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struct trm_target_info tinfo; /* 10 bytes */
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u_int16_t MaxCommand;
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u_int8_t DevMode;
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u_int8_t AdpMode;
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u_int8_t IdentifyMsg;
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u_int8_t Reserved[3]; /*for dword alignment */
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u_int8_t DCBstatus; /* DCB status */
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/*u_int8_t Reserved[3]; for dword alignment */
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struct trm_target_info tinfo; /* 10 bytes */
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struct _DCB *pNextDCB;
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};
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typedef struct _DCB TRM_DCB, *PDCB;
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@ -231,11 +227,18 @@ typedef struct _DCB TRM_DCB, *PDCB;
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*/
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struct _ACB
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{
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device_t dev;
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bus_space_tag_t tag;
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bus_space_handle_t bsh;
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bus_dma_tag_t parent_dmat;
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bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
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struct _ACB *pNextACB;
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bus_dma_tag_t srb_dmat;
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bus_dma_tag_t sense_dmat; /* dmat for sense buffer */
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bus_dmamap_t sense_dmamap;
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bus_dmamap_t srb_dmamap;
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bus_addr_t sense_busaddr;
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struct scsi_sense_data *sense_buffers;
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struct resource *iores, *irq;
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void *ih;
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/*
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@ -244,27 +247,20 @@ struct _ACB
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struct cam_sim *psim;
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struct cam_path *ppath;
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TRM_SRB SRB_array[MAX_SRB_CNT]; /* */
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TRM_SRB TmpSRB;
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PSRB pTmpSRB;
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PSRB RevSRB;
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TRM_SRB TmpSRB;
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TRM_DCB DCBarray[16][8];
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u_int32_t srb_physbase;
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PSRB pFreeSRB;
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PDCB pActiveDCB;
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PDCB pLinkDCB;
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PDCB pDCBRunRobin;
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PDCB pDCB[16][8];
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u_int16_t max_id;
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u_int16_t max_lun;
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u_int16_t IOPortBase;
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u_int16_t AdapterUnit; /*; nth Adapter this driver */
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u_int8_t msgin123[4];
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u_int8_t scan_devices[16][8];
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@ -276,7 +272,8 @@ struct _ACB
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u_int8_t TagMaxNum;
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u_int8_t Config;
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u_int8_t Reserved[2]; /* for dword alignment */
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u_int8_t AdaptType;
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u_int8_t AdapterUnit; /* nth Adapter this driver */
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};
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typedef struct _ACB TRM_ACB, *PACB;
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/*
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@ -322,6 +319,11 @@ typedef struct _ACB TRM_ACB, *PACB;
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*/
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#define ABORT_DEV_ 0x00000001
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/*
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* ---DCB status
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*/
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#define DS_IN_QUEUE 0x00000001
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/*
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* ---SRB status
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*/
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@ -414,12 +416,12 @@ typedef struct _ACB TRM_ACB, *PACB;
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#define MSG_LINK_CMD_COMPL 0x0A
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#define MSG_LINK_CMD_COMPL_FLG 0x0B
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#define MSG_BUS_RESET 0x0C
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#define MSG_ABORT_TAG 0x0D
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/* #define MSG_ABORT_TAG 0x0D */
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#define MSG_SIMPLE_QTAG 0x20
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#define MSG_HEAD_QTAG 0x21
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#define MSG_ORDER_QTAG 0x22
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#define MSG_IGNOREWIDE 0x23
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#define MSG_IDENTIFY 0x80
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/* #define MSG_IDENTIFY 0x80 */
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#define MSG_HOST_ID 0xC0
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/* bus wide length */
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#define MSG_EXT_WDTR_BUS_8_BIT 0x00
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@ -716,6 +718,7 @@ typedef struct _EEprom {
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#define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */
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#define FILTER_DISABLE 0x08 /* Disable SCSI data filter */
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#define ACTIVE_NEG 0x02 /* Enable active negation */
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#define ACTIVE_HISLEW 0x01 /* Enable high slew rate (3/6 ns) */
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/*
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***************************************
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*/
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@ -778,19 +781,23 @@ typedef struct _EEprom {
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/*
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***************************************
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*/
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#define TRMREG_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */
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#define TRMREG_SCSI_TCR00 0x9C /* SCSI Target Control 0 (R/W) */
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/* ######### */
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#define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */
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#define TCR0_SYNC_NEGO_DONE 0x4000 /* Synchronous nego done*/
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#define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS synchronous*/
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#define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE synchronous*/
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#define TCR0_ENABLE_ALT 0x0800 /* Enable alternate synchronous */
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#define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */
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#define TCR0_DO_WIDE_NEGO 0x80 /* Do wide NEGO */
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#define TCR0_DO_SYNC_NEGO 0x40 /* Do sync NEGO */
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#define TCR0_DISCONNECT_EN 0x20 /* Disconnection enable */
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#define TCR0_OFFSET_MASK 0x1F /* Offset number */
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/*
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***************************************
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*/
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#define TRMREG_SCSI_TCR01 0x9D /* SCSI Target Control 0 (R/W) */
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/* ######### */
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#define TCR0_ENABLE_LVDS 0xF8 /* LVD */
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#define TCR0_ENABLE_WIDE 0xF9 /* SE */
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/*
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****************************************
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*/
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#define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */
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#define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */
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#define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */
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#define TCR0_OFFSET_MASK 0x001F /* Offset number */
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/*
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***************************************
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*/
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@ -932,7 +939,7 @@ typedef struct NVRAM_STRUC {
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u_int8_t NvramVendorID[2]; /*5,6 Vendor ID */
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u_int8_t NvramDeviceID[2]; /*7,8 Device ID */
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u_int8_t NvramReserved; /*9 Reserved */
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NVRAMTARGETTYPE NvramTarget[MAX_TARGETS];/* *10,11,12,13
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NVRAMTARGETTYPE NvramTarget[TRM_MAX_TARGETS];/* *10,11,12,13
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*14,15,16,17 * ....
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* ....
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*70,71,72,73
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@ -956,7 +963,7 @@ typedef struct NVRAM_STRUC {
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#define NO_SEEK 0x00000010
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#define LUN_CHECK 0x00000020
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/* Nvram Adapter Cfg bits definition */
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/* Nvram Adapter NvramChannelCfg bits definition */
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#define NAC_SCANLUN 0x20 /* Include LUN as BIOS device*/
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#define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */
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#define NAC_GREATER_1G 0x02 /* > 1G support enable */
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