From f670022acb3c892024f7c5435b93de145c69ea30 Mon Sep 17 00:00:00 2001 From: ed Date: Fri, 24 Nov 2017 13:51:59 +0000 Subject: [PATCH] Set CP15BEN in SCTLR to make memory barriers work in 32-bit mode. Binaries generated by Clang for ARMv6 may contain these instructions: MCR p15, 0, , c7, c10, 5 These instructions are deprecated as of ARMv7, which is why modern processors have a way of toggling support for them. On FreeBSD/arm64 we currently disable support for these instructions, meaning that if 32-bit executables with these instructions are run, they would crash with SIGILL. This is likely not what we want. Reviewed by: andrew Differential Revision: https://reviews.freebsd.org/D13145 --- sys/arm64/arm64/locore.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S index f324aa5326ed..a6a072e8083a 100644 --- a/sys/arm64/arm64/locore.S +++ b/sys/arm64/arm64/locore.S @@ -628,11 +628,12 @@ sctlr_set: /* Bits to set */ .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ - SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | SCTLR_M) + SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \ + SCTLR_M | SCTLR_CP15BEN) sctlr_clear: /* Bits to clear */ .quad (SCTLR_EE | SCTLR_EOE | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ - SCTLR_ITD | SCTLR_THEE | SCTLR_CP15BEN | SCTLR_A) + SCTLR_ITD | SCTLR_THEE | SCTLR_A) .globl abort abort: