- Update some comments regarding hardware details of the 8169 and
note the existence of the 8169S and 8110S components. (The 8169 is just a MAC, the 8169S and 8110S contain both a MAC and PHY.) - Properly handle list and buffer addresses as 64-bit. The RX and TX DMA list addresses should be bus_addr_t's. Added RL_ADDR_HI() and RL_ADDR_LO() macros to obtain values for writing into chip registers. - Set a slightly different TIMERINT value for 8169 NICs for improved performance. - Change left out of previous commit log: added some additional hardware rev codes for other 10/100 chips and for the 8169S/8110S 'rev C' gigE MACs.
This commit is contained in:
Bill Paul
parent
96e934df56
commit
f6bb113e42
@ -80,9 +80,9 @@
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* the 8139 lets you directly access the on-board PHY registers. We need
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* to select which interface to use depending on the chip type.
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*
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* Fast forward a few years. RealTek how has a new chip called the
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* Fast forward a few years. RealTek now has a new chip called the
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* 8139C+ which at long last implements descriptor-based DMA. Not
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* only that, in supports RX and TX TCP/IP checksum offload, VLAN
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* only that, it supports RX and TX TCP/IP checksum offload, VLAN
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* tagging and insertion, TCP large send and 64-bit addressing.
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* Better still, it allows arbitrary byte alignments for RX and
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* TX buffers, meaning no copying is necessary on any architecture.
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@ -96,26 +96,36 @@
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* mode has to be enabled by setting the appropriate bits in the C+
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* command register. The PHY access mechanism appears to be unchanged.
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*
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* The 8169 is a 10/100/1000 ethernet MAC with built-in tri-speed
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* copper PHY. It has almost the same programming API as the C+ mode
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* of the 8139C+, with a couple of minor changes and additions: the
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* TX start register is located at a different offset, and there are
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* additional registers for GMII PHY status and control, as well as
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* TBI-mode status and control. There is also a maximum RX packet
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* size register to allow the chip to receive jumbo frames. The
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* 8169 can only be programmed in C+ mode: the old 8139 programming
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* The 8169 is a 10/100/1000 ethernet MAC. It has almost the same
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* programming API as the C+ mode of the 8139C+, with a couple of
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* minor changes and additions: TX start register and timer interrupt
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* register are located at different offsets, and there are additional
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* registers for GMII PHY status and control, as well as TBI-mode
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* status and control. There is also a maximum RX packet size
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* register to allow the chip to receive jumbo frames. The 8169
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* can only be programmed in C+ mode: the old 8139 programming
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* method isn't supported with this chip. Also, RealTek has a LOM
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* (LAN On Motherboard) gigabit MAC chip called the RTL8110S which
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* I believe to be register compatible with the 8169.
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* I believe to be register compatible with the 8169. Unlike the
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* 8139C+, the 8169 can have up to 1024 descriptors per DMA ring.
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* The reference 8169 board design uses a Marvell 88E1000 'Alaska'
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* copper PHY.
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*
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* Unfortunately, RealTek has not released a programming manual for
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* the 8169 or 8110 yet. The datasheet for the 8139C+ provides most
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* The 8169S and 8110S are newer versions of the 8169. Available
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* in both 32-bit and 64-bit forms, these devices have built-in
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* copper 10/100/1000 PHYs. The 8110S is a lan-on-motherboard chip
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* that is pin-for-pin compatible with the 8100. Unfortunately,
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* RealTek has not released programming manuals for the 8169S and
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* 8110S yet. The datasheet for the original 8169 provides most
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* of the information, but you must refer to RealTek's 8169 Linux
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* driver to fill in the gaps.
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* driver to fill in the gaps. Mostly, it appears that the built-in
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* PHY requires some special initialization. The original 8169
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* datasheet and the 8139C+ datasheet can be obtained from
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* http://www.freebsd.org/~wpaul/RealTek.
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*
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* This driver now supports both the old 8139 and new 8139C+
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* programming models. We detect the 8139C+ by looking for a PCI
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* revision ID of 0x20 or higher, and we detect the 8169 by its
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* programming models. We detect the 8139C+ by looking for the
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* corresponding hardware rev bits, and we detect the 8169 by its
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* PCI ID. Two new NIC type codes, RL_8139CPLUS and RL_8169 have
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* been added to distinguish the chips at runtime. Separate RX and
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* TX handling routines have been added to handle C+ mode, which
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@ -1122,8 +1132,8 @@ rl_dma_map_desc(arg, segs, nseg, mapsize, error)
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return;
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}
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cmdstat = segs[i].ds_len;
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d->rl_bufaddr_lo = htole32(segs[i].ds_addr);
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d->rl_bufaddr_hi = 0;
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d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
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d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
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if (i == 0)
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cmdstat |= RL_TDESC_CMD_SOF;
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else
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@ -1834,6 +1844,10 @@ rl_rxeofcplus(sc)
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m->m_pkthdr.len = m->m_len = total_len;
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m->m_pkthdr.rcvif = ifp;
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/* Do RX checksumming if enabled */
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if (ifp->if_capenable & IFCAP_RXCSUM) {
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/* Check IP header checksum */
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if (rxstat & RL_RDESC_STAT_PROTOID)
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m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
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@ -1849,6 +1863,7 @@ rl_rxeofcplus(sc)
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CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
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m->m_pkthdr.csum_data = 0xffff;
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}
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}
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if (rxvlan & RL_RDESC_VLANCTL_TAG)
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VLAN_INPUT_TAG(ifp, m,
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@ -2734,13 +2749,15 @@ rl_init(xsc)
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(ifp->if_capenable & IFCAP_RXCSUM ?
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RL_CPLUSCMD_RXCSUM_ENB : 0));
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CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 0);
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CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
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RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
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CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
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sc->rl_ldata.rl_rx_list_addr);
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RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
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CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 0);
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CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
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RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
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CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
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sc->rl_ldata.rl_tx_list_addr);
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RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
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CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, RL_EARLYTXTHRESH_CNT);
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@ -2753,7 +2770,7 @@ rl_init(xsc)
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*/
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if (sc->rl_type == RL_8169)
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CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x400);
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CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
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else
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CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
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@ -593,6 +593,9 @@ struct rl_stats {
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RL_RDESC_STAT_FRAGLEN)
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#define RL_PKTSZ(x) ((x) >> 3)
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#define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF)
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#define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32)
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struct rl_softc;
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struct rl_dmaload_arg {
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@ -615,15 +618,15 @@ struct rl_list_data {
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bus_dma_tag_t rl_stag; /* stats mapping tag */
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bus_dmamap_t rl_smap; /* stats map */
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struct rl_stats *rl_stats;
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u_int32_t rl_stats_addr;
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bus_addr_t rl_stats_addr;
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bus_dma_tag_t rl_rx_list_tag;
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bus_dmamap_t rl_rx_list_map;
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struct rl_desc *rl_rx_list;
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u_int32_t rl_rx_list_addr;
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bus_addr_t rl_rx_list_addr;
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bus_dma_tag_t rl_tx_list_tag;
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bus_dmamap_t rl_tx_list_map;
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struct rl_desc *rl_tx_list;
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u_int32_t rl_tx_list_addr;
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bus_addr_t rl_tx_list_addr;
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};
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struct rl_softc {
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