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Explicitly clear 1000baseT control register for F1 PHY used in

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AR8132 FastEthernet controller. The PHY has no ability to
establish a gigabit link. Previously only link parters which
support down-shifting was able to establish link.
This change should fix a long standing link establishment issue of
AR8132.

PR:		kern/156935
MFC after:	1 week
This commit is contained in:
Pyun YongHyeon 2011-05-12 17:11:31 +00:00
parent 76db9ccfbe
commit f6d9580d0d
1 changed files with 12 additions and 0 deletions
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12
sys/dev/mii/atphy.c
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@ -359,6 +359,18 @@ atphy_setmedia(struct mii_softc *sc, int media)
(EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
GTCR_ADV_1000THDX);
else if (sc->mii_mpd_model == MII_MODEL_xxATHEROS_F1) {
/*
* AR8132 has 10/100 PHY and the PHY uses the same
* model number of F1 gigabit PHY. The PHY has no
* ability to establish gigabit link so explicitly
* disable 1000baseT configuration for the PHY.
* Otherwise, there is a case that atphy(4) could
* not establish a link against gigabit link partner
* unless the link partner supports down-shifting.
*/
PHY_WRITE(sc, MII_100T2CR, 0);
}
PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
return (EJUSTRETURN);