Add more interrupts handled for booke.
e500mc, e5500, and e6500 all use the normal FPU, with the same behavior as AIM hardware. e6500 also supports Altivec, so, although we don't yet have e6500 hardware to test on, add these IVORs as well. Theoretically, since it boots the same as a e5500, it should work, single-threaded, single-core, with full altivec support as of this commit. With this commit, and some other patches to be committed shortly FreeBSD now boots on the P5020, single-core, all the way to user space, and should boot just fine on e500mc. Relnotes: Yes (e500mc, e5500 support) Sponsored by: Alex Perez/Inertial Computing
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@ -142,7 +142,7 @@ __FBSDID("$FreeBSD$");
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#ifdef MPC85XX
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#if defined(MPC85XX) || defined(QORIQ_DPAA)
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#include <powerpc/mpc85xx/mpc85xx.h>
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#endif
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@ -183,6 +183,7 @@ extern void *int_data_storage;
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extern void *int_instr_storage;
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extern void *int_external_input;
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extern void *int_alignment;
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extern void *int_fpu;
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extern void *int_program;
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extern void *int_syscall;
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extern void *int_decrementer;
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@ -191,6 +192,8 @@ extern void *int_watchdog;
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extern void *int_data_tlb_error;
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extern void *int_inst_tlb_error;
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extern void *int_debug;
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extern void *int_vec;
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extern void *int_vecast;
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#ifdef HWPMC_HOOKS
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extern void *int_performance_counter;
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#endif
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@ -234,6 +237,15 @@ ivor_setup(void)
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#ifdef HWPMC_HOOKS
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SET_TRAP(SPR_IVOR35, int_performance_counter);
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#endif
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switch ((mfpvr() >> 16) & 0xffff) {
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case FSL_E6500:
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SET_TRAP(SPR_IVOR32, int_vec);
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SET_TRAP(SPR_IVOR33, int_vecast);
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/* FALLTHROUGH */
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case FSL_E500mc:
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case FSL_E5500:
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SET_TRAP(SPR_IVOR7, int_fpu);
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}
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}
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static int
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@ -393,12 +393,19 @@
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.globl CNAME(interrupt_vector_base)
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.align 5
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interrupt_vector_base:
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/*****************************************************************************
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* Catch-all handler to handle uninstalled IVORs
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****************************************************************************/
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INTERRUPT(int_unknown)
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STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1)
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FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_RSVD)
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b trap_common
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/*****************************************************************************
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* Critical input interrupt
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****************************************************************************/
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INTERRUPT(int_critical_input)
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STANDARD_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1)
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STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1)
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FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_CRIT)
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addi %r3, %r1, 8
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bl CNAME(powerpc_interrupt)
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@ -459,6 +466,12 @@ INTERRUPT(int_program)
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b trap_common
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INTERRUPT(int_fpu)
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STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1)
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FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_FPU)
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b trap_common
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/*****************************************************************************
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* System call
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****************************************************************************/
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@ -497,6 +510,24 @@ INTERRUPT(int_watchdog)
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b trap_common
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/*****************************************************************************
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* Altivec Unavailable interrupt
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****************************************************************************/
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INTERRUPT(int_vec)
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STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1)
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FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_VEC)
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b trap_common
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/*****************************************************************************
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* Watchdog interrupt
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****************************************************************************/
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INTERRUPT(int_vecast)
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STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1)
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FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_VECAST_E)
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b trap_common
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#ifdef HWPMC_HOOKS
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/*****************************************************************************
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* PMC Interrupt
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@ -86,6 +86,7 @@
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#define EXC_ITMISS 0x1200 /* Instruction TLB Miss */
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#define EXC_APU 0x1300 /* Auxiliary Processing Unit */
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#define EXC_DEBUG 0x2f10 /* Debug trap */
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#define EXC_VECAST_E 0x2f20 /* Altivec Assist (Book-E) */
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#define EXC_LAST 0x2f00 /* Last possible exception vector */
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