Add PrimeCell UART (PL011) driver
Obtained from: Semihalf
This commit is contained in:
Oleksandr Tymoshenko
parent
ec9a9cf1e0
commit
f70f23cc3e
@ -2065,6 +2065,7 @@ dev/uart/uart_bus_scc.c optional uart scc
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dev/uart/uart_core.c optional uart
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dev/uart/uart_dbg.c optional uart gdb
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dev/uart/uart_dev_ns8250.c optional uart uart_ns8250
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dev/uart/uart_dev_pl011.c optional uart pl011
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dev/uart/uart_dev_quicc.c optional uart quicc
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dev/uart/uart_dev_sab82532.c optional uart uart_sab82532
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dev/uart/uart_dev_sab82532.c optional uart scc
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@ -70,6 +70,7 @@ extern struct uart_class uart_sab82532_class __attribute__((weak));
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extern struct uart_class uart_sbbc_class __attribute__((weak));
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extern struct uart_class uart_z8530_class __attribute__((weak));
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extern struct uart_class uart_lpc_class __attribute__((weak));
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extern struct uart_class uart_pl011_class __attribute__((weak));
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#ifdef PC98
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struct uart_class *uart_pc98_getdev(u_long port);
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@ -105,6 +105,8 @@ uart_fdt_probe(device_t dev)
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sc->sc_class = &uart_ns8250_class;
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else if (ofw_bus_is_compatible(dev, "lpc,uart"))
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sc->sc_class = &uart_lpc_class;
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else if (ofw_bus_is_compatible(dev, "arm,pl011"))
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sc->sc_class = &uart_pl011_class;
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else
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return (ENXIO);
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@ -188,6 +190,8 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
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class = &uart_lpc_class;
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if (fdt_is_compatible(node, "ns16550"))
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class = &uart_ns8250_class;
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if (fdt_is_compatible(node, "arm,pl011"))
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class = &uart_pl011_class;
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di->bas.chan = 0;
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di->bas.regshft = (u_int)shift;
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436
sys/dev/uart/uart_dev_pl011.c
Normal file
436
sys/dev/uart/uart_dev_pl011.c
Normal file
@ -0,0 +1,436 @@
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/*-
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* Copyright (c) 2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include "uart_if.h"
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#include <sys/kdb.h>
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/* PL011 UART registers and masks*/
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#define UART_DR 0x00 /* Data register */
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#define DR_FE (1 << 8) /* Framing error */
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#define DR_PE (1 << 9) /* Parity error */
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#define DR_BE (1 << 10) /* Break error */
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#define DR_OE (1 << 11) /* Overrun error */
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#define UART_FR 0x06 /* Flag register */
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#define FR_RXFF (1 << 6) /* Receive FIFO/reg full */
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#define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */
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#define UART_IBRD 0x09 /* Integer baud rate register */
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#define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */
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#define UART_FBRD 0x0a /* Fractional baud rate register */
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#define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */
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#define UART_LCR_H 0x0b /* Line control register */
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#define LCR_H_WLEN8 (0x3 << 5)
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#define LCR_H_WLEN7 (0x2 << 5)
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#define LCR_H_WLEN6 (0x1 << 5)
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#define LCR_H_FEN (1 << 4) /* FIFO mode enable */
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#define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */
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#define LCR_H_EPS (1 << 2) /* Even parity select */
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#define LCR_H_PEN (1 << 1) /* Parity enable */
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#define UART_CR 0x0c /* Control register */
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#define CR_RXE (1 << 9) /* Receive enable */
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#define CR_TXE (1 << 8) /* Transmit enable */
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#define CR_UARTEN (1 << 0) /* UART enable */
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#define UART_IMSC 0x0e /* Interrupt mask set/clear register */
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#define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */
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#define UART_RIS 0x0f /* Raw interrupt status register */
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#define UART_RXREADY (1 << 4) /* RX buffer full */
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#define UART_TXEMPTY (1 << 5) /* TX buffer empty */
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#define RIS_FE (1 << 7) /* Framing error interrupt status */
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#define RIS_PE (1 << 8) /* Parity error interrupt status */
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#define RIS_BE (1 << 9) /* Break error interrupt status */
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#define RIS_OE (1 << 10) /* Overrun interrupt status */
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#define UART_MIS 0x10 /* Masked interrupt status register */
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#define UART_ICR 0x11 /* Interrupt clear register */
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/*
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* FIXME: actual register size is SoC-dependent, we need to handle it
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*/
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#define __uart_getreg(bas, reg) \
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bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
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#define __uart_setreg(bas, reg, value) \
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bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
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/*
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* Low-level UART interface.
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*/
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static int uart_pl011_probe(struct uart_bas *bas);
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static void uart_pl011_init(struct uart_bas *bas, int, int, int, int);
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static void uart_pl011_term(struct uart_bas *bas);
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static void uart_pl011_putc(struct uart_bas *bas, int);
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static int uart_pl011_rxready(struct uart_bas *bas);
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static int uart_pl011_getc(struct uart_bas *bas, struct mtx *);
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static struct uart_ops uart_pl011_ops = {
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.probe = uart_pl011_probe,
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.init = uart_pl011_init,
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.term = uart_pl011_term,
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.putc = uart_pl011_putc,
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.rxready = uart_pl011_rxready,
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.getc = uart_pl011_getc,
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};
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static int
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uart_pl011_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static void
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uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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uint32_t ctrl, line;
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uint32_t baud;
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/* Mask all interrupts */
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__uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) &
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~IMSC_MASK_ALL);
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/*
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* Zero all settings to make sure
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* UART is disabled and not configured
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*/
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ctrl = line = 0x0;
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__uart_setreg(bas, UART_CR, ctrl);
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/* As we know UART is disabled we may setup the line */
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switch (databits) {
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case 7:
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line |= LCR_H_WLEN7;
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break;
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case 6:
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line |= LCR_H_WLEN6;
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break;
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case 8:
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default:
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line |= LCR_H_WLEN8;
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break;
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}
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/* TODO: Calculate divisors */
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baud = (0x1 << 16) | 0x28;
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if (stopbits == 2)
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line |= LCR_H_STP2;
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else
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line &= ~LCR_H_STP2;
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if (parity)
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line |= LCR_H_PEN;
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else
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line &= ~LCR_H_PEN;
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/* Configure the rest */
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line &= ~LCR_H_FEN;
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ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);
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__uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 16)) & IBRD_BDIVINT);
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__uart_setreg(bas, UART_FBRD, (uint32_t)(baud) & FBRD_BDIVFRAC);
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/* Add config. to line before reenabling UART */
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__uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) &
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~0xff) | line);
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__uart_setreg(bas, UART_CR, ctrl);
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}
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static void
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uart_pl011_term(struct uart_bas *bas)
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{
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}
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static void
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uart_pl011_putc(struct uart_bas *bas, int c)
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{
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while (!(__uart_getreg(bas, UART_FR) & FR_TXFE))
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;
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__uart_setreg(bas, UART_DR, c & 0xff);
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}
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static int
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uart_pl011_rxready(struct uart_bas *bas)
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{
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return (__uart_getreg(bas, UART_FR) & FR_RXFF);
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}
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static int
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uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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while (!uart_pl011_rxready(bas))
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;
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c = __uart_getreg(bas, UART_DR) & 0xff;
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return (c);
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}
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/*
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* High-level UART interface.
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*/
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struct uart_pl011_softc {
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struct uart_softc base;
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uint8_t fcr;
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uint8_t ier;
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uint8_t mcr;
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uint8_t ier_mask;
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uint8_t ier_rxbits;
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};
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static int uart_pl011_bus_attach(struct uart_softc *);
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static int uart_pl011_bus_detach(struct uart_softc *);
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static int uart_pl011_bus_flush(struct uart_softc *, int);
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static int uart_pl011_bus_getsig(struct uart_softc *);
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static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int uart_pl011_bus_ipend(struct uart_softc *);
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static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int);
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static int uart_pl011_bus_probe(struct uart_softc *);
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static int uart_pl011_bus_receive(struct uart_softc *);
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static int uart_pl011_bus_setsig(struct uart_softc *, int);
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static int uart_pl011_bus_transmit(struct uart_softc *);
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static kobj_method_t uart_pl011_methods[] = {
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KOBJMETHOD(uart_attach, uart_pl011_bus_attach),
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KOBJMETHOD(uart_detach, uart_pl011_bus_detach),
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KOBJMETHOD(uart_flush, uart_pl011_bus_flush),
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KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig),
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KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl),
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KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend),
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KOBJMETHOD(uart_param, uart_pl011_bus_param),
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KOBJMETHOD(uart_probe, uart_pl011_bus_probe),
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KOBJMETHOD(uart_receive, uart_pl011_bus_receive),
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KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig),
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KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit),
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{ 0, 0 }
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};
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struct uart_class uart_pl011_class = {
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"uart_pl011",
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uart_pl011_methods,
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sizeof(struct uart_pl011_softc),
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.uc_ops = &uart_pl011_ops,
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.uc_range = 0x48,
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.uc_rclk = 0
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};
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static int
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uart_pl011_bus_attach(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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bas = &sc->sc_bas;
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/* Enable RX & TX interrupts */
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__uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY));
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/* Clear RX & TX interrupts */
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__uart_setreg(bas, UART_ICR, IMSC_MASK_ALL);
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sc->sc_rxfifosz = 1;
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sc->sc_txfifosz = 1;
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return (0);
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}
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static int
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uart_pl011_bus_detach(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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uart_pl011_bus_flush(struct uart_softc *sc, int what)
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{
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return (0);
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}
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static int
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uart_pl011_bus_getsig(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
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{
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struct uart_bas *bas;
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int error;
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bas = &sc->sc_bas;
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error = 0;
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uart_lock(sc->sc_hwmtx);
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switch (request) {
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case UART_IOCTL_BREAK:
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break;
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case UART_IOCTL_BAUD:
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*(int*)data = 115200;
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break;
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default:
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error = EINVAL;
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break;
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}
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uart_unlock(sc->sc_hwmtx);
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return (error);
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}
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static int
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uart_pl011_bus_ipend(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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int ipend;
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uint32_t ints;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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ints = __uart_getreg(bas, UART_MIS);
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ipend = 0;
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if (ints & UART_RXREADY)
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ipend |= SER_INT_RXREADY;
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if (ints & RIS_BE)
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ipend |= SER_INT_BREAK;
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if (ints & RIS_OE)
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ipend |= SER_INT_OVERRUN;
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if (ints & UART_TXEMPTY) {
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if (sc->sc_txbusy)
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ipend |= SER_INT_TXIDLE;
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__uart_setreg(bas, UART_IMSC, UART_RXREADY);
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}
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uart_unlock(sc->sc_hwmtx);
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return (ipend);
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}
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static int
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uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits,
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int stopbits, int parity)
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{
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uart_lock(sc->sc_hwmtx);
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uart_pl011_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static int
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uart_pl011_bus_probe(struct uart_softc *sc)
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{
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device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");
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return (0);
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}
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static int
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uart_pl011_bus_receive(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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int rx;
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uint32_t ints, xc;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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ints = __uart_getreg(bas, UART_MIS);
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while (ints & UART_RXREADY) {
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if (uart_rx_full(sc)) {
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sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
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break;
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}
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xc = __uart_getreg(bas, UART_DR);
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rx = xc & 0xff;
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if (xc & DR_FE)
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rx |= UART_STAT_FRAMERR;
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if (xc & DR_PE)
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rx |= UART_STAT_PARERR;
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__uart_setreg(bas, UART_ICR, UART_RXREADY);
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uart_rx_put(sc, rx);
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ints = __uart_getreg(bas, UART_MIS);
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}
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static int
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uart_pl011_bus_setsig(struct uart_softc *sc, int sig)
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{
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return (0);
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}
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static int
|
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uart_pl011_bus_transmit(struct uart_softc *sc)
|
||||
{
|
||||
struct uart_bas *bas;
|
||||
int i;
|
||||
|
||||
bas = &sc->sc_bas;
|
||||
uart_lock(sc->sc_hwmtx);
|
||||
|
||||
for (i = 0; i < sc->sc_txdatasz; i++) {
|
||||
__uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);
|
||||
uart_barrier(bas);
|
||||
}
|
||||
sc->sc_txbusy = 1;
|
||||
__uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY));
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
|
||||
return (0);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user