o Fix style.
o Remove set but not used variable. Sponsored by: DARPA, AFRL
This commit is contained in:
Ruslan Bukin
parent
1b664b2eea
commit
f73b677d04
@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2012,2013 Bjoern A. Zeeb
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* Copyright (c) 2012, 2013 Bjoern A. Zeeb
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* Copyright (c) 2014 Robert N. M. Watson
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* All rights reserved.
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*
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@ -135,6 +135,7 @@ a_onchip_fifo_mem_core_write(struct resource *res, uint32_t off,
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DPRINTF("[%s:%d] FIFOW %s 0x%08x = 0x%08x\n", f, l, desc, off, val4);
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bus_write_4(res, off, val4);
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}
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static inline uint32_t
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a_onchip_fifo_mem_core_read(struct resource *res, uint32_t off,
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const char *desc, const char *f, const int l)
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@ -143,6 +144,7 @@ a_onchip_fifo_mem_core_read(struct resource *res, uint32_t off,
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val4 = le32toh(bus_read_4(res, off));
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DPRINTF("[%s:%d] FIFOR %s 0x%08x = 0x%08x\n", f, l, desc, off, val4);
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return (val4);
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}
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@ -285,6 +287,7 @@ csr_read_4(struct atse_softc *sc, uint32_t reg, const char *f, const int l)
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val4 = le32toh(bus_read_4(sc->atse_mem_res, reg * 4));
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DPRINTF("[%s:%d] CSR R %s 0x%08x (0x%08x) = 0x%08x\n", f, l,
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"atse_mem_res", reg, reg * 4, val4);
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return (val4);
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}
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@ -315,6 +318,7 @@ pxx_read_2(struct atse_softc *sc, bus_addr_t bmcr, uint32_t reg, const char *f,
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val = le32toh(val4) & 0x0000ffff;
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DPRINTF("[%s:%d] %s R %s 0x%08x (0x%08jx) = 0x%04x\n", f, l, s,
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"atse_mem_res", reg, (bmcr + reg) * 4, val);
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return (val);
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}
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@ -343,6 +347,7 @@ atse_tx_locked(struct atse_softc *sc, int *sent)
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{
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struct mbuf *m;
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uint32_t val4, fill_level;
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int leftm;
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int c;
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ATSE_LOCK_ASSERT(sc);
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@ -393,15 +398,13 @@ atse_tx_locked(struct atse_softc *sc, int *sent)
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/* Set EOP *before* writing the last symbol. */
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if (sc->atse_tx_m_offset >= (sc->atse_tx_buf_len - 4) &&
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fill_level < AVALON_FIFO_TX_BASIC_OPTS_DEPTH) {
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int leftm;
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uint32_t x;
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/* Set EndOfPacket. */
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val4 = A_ONCHIP_FIFO_MEM_CORE_EOP;
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/* Set EMPTY. */
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leftm = sc->atse_tx_buf_len - sc->atse_tx_m_offset;
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val4 |= ((4 - leftm) << A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT);
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x = val4;
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ATSE_TX_META_WRITE(sc, val4);
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/* Write last symbol. */
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@ -440,7 +443,7 @@ atse_start_locked(struct ifnet *ifp)
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return;
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#if 1
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/*
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/*
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* Disable the watchdog while sending, we are batching packets.
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* Though we should never reach 5 seconds, and are holding the lock,
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* but who knows.
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@ -485,8 +488,8 @@ atse_start(struct ifnet *ifp)
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static int
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atse_stop_locked(struct atse_softc *sc)
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{
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struct ifnet *ifp;
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uint32_t mask, val4;
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struct ifnet *ifp;
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int i;
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ATSE_LOCK_ASSERT(sc);
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@ -527,8 +530,8 @@ atse_stop_locked(struct atse_softc *sc)
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static uint8_t
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atse_mchash(struct atse_softc *sc __unused, const uint8_t *addr)
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{
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int i, j;
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uint8_t x, y;
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int i, j;
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x = 0;
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for (i = 0; i < ETHER_ADDR_LEN; i++) {
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@ -537,14 +540,15 @@ atse_mchash(struct atse_softc *sc __unused, const uint8_t *addr)
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y ^= (addr[i] >> j) & 0x01;
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x |= (y << i);
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}
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return (x);
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}
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static int
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atse_rxfilter_locked(struct atse_softc *sc)
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{
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struct ifnet *ifp;
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struct ifmultiaddr *ifma;
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struct ifnet *ifp;
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uint32_t val4;
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int i;
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@ -567,7 +571,7 @@ atse_rxfilter_locked(struct atse_softc *sc)
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for (i = 0; i <= MHASH_LEN; i++)
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CSR_WRITE_4(sc, MHASH_START + i, 0x1);
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} else {
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/*
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/*
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* Can hold MHASH_LEN entries.
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* XXX-BZ bitstring.h would be more general.
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*/
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@ -634,8 +638,9 @@ atse_ethernet_option_bits_read(device_t dev)
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error = atse_ethernet_option_bits_read_fdt(dev);
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if (error == 0)
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return (0);
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device_printf(dev, "Cannot read Ethernet addresses from flash.\n");
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return (error);
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}
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@ -789,9 +794,9 @@ atse_set_eth_address(struct atse_softc *sc, int n)
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static int
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atse_reset(struct atse_softc *sc)
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{
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int i;
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uint32_t val4, mask;
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uint16_t val;
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int i;
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/* 1. External PHY Initialization using MDIO. */
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/*
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@ -820,6 +825,7 @@ atse_reset(struct atse_softc *sc)
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val = PCS_READ_2(sc, PCS_CONTROL);
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val |= PCS_CONTROL_RESET;
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PCS_WRITE_2(sc, PCS_CONTROL, val);
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/* Wait for reset bit to clear; i=100 is excessive. */
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for (i = 0; i < 100; i++) {
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val = PCS_READ_2(sc, PCS_CONTROL);
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@ -827,6 +833,7 @@ atse_reset(struct atse_softc *sc)
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break;
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DELAY(10);
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}
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if ((val & PCS_CONTROL_RESET) != 0) {
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device_printf(sc->atse_dev, "PCS reset timed out.\n");
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return (ENXIO);
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@ -877,7 +884,7 @@ atse_reset(struct atse_softc *sc)
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CSR_WRITE_4(sc, BASE_CFG_PAUSE_QUANT, 0xFFFF);
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val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
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/*
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/*
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* If 1000BASE-X/SGMII PCS is initialized, set the ETH_SPEED (bit 3)
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* and ENA_10 (bit 25) in command_config register to 0. If half duplex
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* is reported in the PHY/PCS status register, set the HD_ENA (bit 10)
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@ -936,7 +943,7 @@ atse_reset(struct atse_softc *sc)
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device_printf(sc->atse_dev, "MAC reset timed out.\n");
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return (ENXIO);
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}
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/* f. Enable MAC transmit and receive datapath. */
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mask = BASE_CFG_COMMAND_CONFIG_TX_ENA|BASE_CFG_COMMAND_CONFIG_RX_ENA;
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val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
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@ -992,7 +999,7 @@ atse_init_locked(struct atse_softc *sc)
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sc->atse_flags &= ATSE_FLAGS_LINK; /* Preserve. */
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#ifdef DEVICE_POLLING
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/* Only enable interrupts if we are not polling. */
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/* Only enable interrupts if we are not polling. */
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if (ifp->if_capenable & IFCAP_POLLING) {
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ATSE_RX_INTR_DISABLE(sc);
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ATSE_TX_INTR_DISABLE(sc);
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@ -1039,7 +1046,6 @@ atse_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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struct ifreq *ifr;
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int error, mask;
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error = 0;
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sc = ifp->if_softc;
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ifr = (struct ifreq *)data;
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@ -1056,7 +1062,7 @@ atse_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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atse_init_locked(sc);
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} else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
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atse_stop_locked(sc);
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sc->atse_if_flags = ifp->if_flags;
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sc->atse_if_flags = ifp->if_flags;
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ATSE_UNLOCK(sc);
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break;
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case SIOCSIFCAP:
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@ -1193,7 +1199,7 @@ atse_tick(void *xsc)
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/*
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* Set media options.
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*/
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static int
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static int
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atse_ifmedia_upd(struct ifnet *ifp)
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{
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struct atse_softc *sc;
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@ -1227,15 +1233,16 @@ atse_update_rx_err(struct atse_softc *sc, uint32_t mask)
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static int
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atse_rx_locked(struct atse_softc *sc)
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{
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struct ifnet *ifp;
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struct mbuf *m;
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uint32_t fill, i, j;
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uint32_t data, meta;
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int rx_npkts = 0;
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struct ifnet *ifp;
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struct mbuf *m;
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int rx_npkts;
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ATSE_LOCK_ASSERT(sc);
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ifp = sc->atse_ifp;
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rx_npkts = 0;
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j = 0;
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meta = 0;
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do {
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@ -1294,7 +1301,7 @@ outer:
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/* XXX-BZ any better counter? */
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if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
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}
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if ((sc->atse_flags & ATSE_FLAGS_SOP_SEEN) == 0)
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{
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sc->atse_flags |= ATSE_FLAGS_SOP_SEEN;
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@ -1403,7 +1410,7 @@ atse_rx_intr(void *arg)
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if (ifp->if_capenable & IFCAP_POLLING) {
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ATSE_UNLOCK(sc);
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return;
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}
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}
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#endif
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atse_intr_debug(sc, "rx");
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@ -1460,7 +1467,7 @@ atse_tx_intr(void *arg)
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if (ifp->if_capenable & IFCAP_POLLING) {
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ATSE_UNLOCK(sc);
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return;
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}
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}
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#endif
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/* XXX-BZ build histogram. */
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@ -1508,7 +1515,7 @@ atse_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
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ATSE_LOCK(sc);
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if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
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ATSE_UNLOCK(sc);
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return (rx_npkts);
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return (rx_npkts);
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}
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sc->atse_rx_cycles = count;
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@ -1658,9 +1665,9 @@ static int
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sysctl_atse_mac_stats_proc(SYSCTL_HANDLER_ARGS)
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{
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struct atse_softc *sc;
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int error, offset, s;
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int error, offset, s;
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sc = arg1;
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sc = arg1;
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offset = arg2;
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s = CSR_READ_4(sc, offset);
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@ -1668,7 +1675,7 @@ sysctl_atse_mac_stats_proc(SYSCTL_HANDLER_ARGS)
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if (error || !req->newptr)
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return (error);
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return (0);
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return (0);
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}
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static struct atse_rx_err_stats_regs {
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@ -1676,12 +1683,12 @@ static struct atse_rx_err_stats_regs {
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const char *descr;
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} atse_rx_err_stats_regs[] = {
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#define ATSE_RX_ERR_FIFO_THRES_EOP 0 /* FIFO threshold reached, on EOP. */
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#define ATSE_RX_ERR_ELEN 1 /* Frame/payload length not valid. */
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#define ATSE_RX_ERR_CRC32 2 /* CRC-32 error. */
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#define ATSE_RX_ERR_FIFO_THRES_TRUNC 3 /* FIFO thresh., truncated frame. */
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#define ATSE_RX_ERR_4 4 /* ? */
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#define ATSE_RX_ERR_5 5 /* / */
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#define ATSE_RX_ERR_FIFO_THRES_EOP 0 /* FIFO threshold reached, on EOP. */
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#define ATSE_RX_ERR_ELEN 1 /* Frame/payload length not valid. */
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#define ATSE_RX_ERR_CRC32 2 /* CRC-32 error. */
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#define ATSE_RX_ERR_FIFO_THRES_TRUNC 3 /* FIFO thresh., truncated frame. */
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#define ATSE_RX_ERR_4 4 /* ? */
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#define ATSE_RX_ERR_5 5 /* / */
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{ "rx_err_fifo_thres_eop",
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"FIFO threshold reached, reported on EOP." },
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@ -1701,9 +1708,9 @@ static int
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sysctl_atse_rx_err_stats_proc(SYSCTL_HANDLER_ARGS)
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{
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struct atse_softc *sc;
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int error, offset, s;
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int error, offset, s;
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sc = arg1;
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sc = arg1;
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offset = arg2;
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s = sc->atse_rx_err[offset];
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@ -1711,7 +1718,7 @@ sysctl_atse_rx_err_stats_proc(SYSCTL_HANDLER_ARGS)
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if (error || !req->newptr)
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return (error);
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return (0);
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return (0);
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}
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static void
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@ -1723,8 +1730,8 @@ atse_sysctl_stats_attach(device_t dev)
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int i;
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sc = device_get_softc(dev);
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sctx = device_get_sysctl_ctx(dev);
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soid = device_get_sysctl_tree(dev);
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sctx = device_get_sysctl_ctx(dev);
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soid = device_get_sysctl_tree(dev);
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/* MAC statistics. */
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for (i = 0; i < nitems(atse_mac_stats_regs); i++) {
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@ -2034,11 +2041,11 @@ atse_miibus_statchg(device_t dev)
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sc = device_get_softc(dev);
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ATSE_LOCK_ASSERT(sc);
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mii = device_get_softc(sc->atse_miibus);
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ifp = sc->atse_ifp;
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if (mii == NULL || ifp == NULL ||
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(ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
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return;
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mii = device_get_softc(sc->atse_miibus);
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ifp = sc->atse_ifp;
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if (mii == NULL || ifp == NULL ||
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(ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
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return;
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val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
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@ -2069,14 +2076,14 @@ atse_miibus_statchg(device_t dev)
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}
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}
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if ((sc->atse_flags & ATSE_FLAGS_LINK) == 0) {
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if ((sc->atse_flags & ATSE_FLAGS_LINK) == 0) {
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/* XXX-BZ need to stop the MAC? */
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return;
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}
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return;
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}
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if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0)
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val4 &= ~BASE_CFG_COMMAND_CONFIG_HD_ENA;
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else
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else
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val4 |= BASE_CFG_COMMAND_CONFIG_HD_ENA;
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/* XXX-BZ flow control? */
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