Add definitions related to the L1D flush operation capability and MSR.
Sponsored by: The FreeBSD Foundation
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@ -427,6 +427,7 @@
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*/
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#define CPUID_STDEXT3_IBPB 0x04000000
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#define CPUID_STDEXT3_STIBP 0x08000000
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#define CPUID_STDEXT3_L1D_FLUSH 0x10000000
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#define CPUID_STDEXT3_ARCH_CAP 0x20000000
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#define CPUID_STDEXT3_SSBD 0x80000000
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@ -478,6 +479,7 @@
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#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
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#define MSR_MTRRcap 0x0fe
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#define MSR_IA32_ARCH_CAP 0x10a
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#define MSR_IA32_FLUSH_CMD 0x10b
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#define MSR_BBL_CR_ADDR 0x116
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#define MSR_BBL_CR_DECC 0x118
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#define MSR_BBL_CR_CTL 0x119
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@ -711,6 +713,9 @@
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/* MSR IA32_PRED_CMD */
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#define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
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/* MSR IA32_FLUSH_CMD */
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#define IA32_FLUSH_CMD_L1D 0x00000001
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/*
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* PAT modes.
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*/
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