Introduce an AR5416 flavour of the IFS and mac usec/timing configuration
used when running the chips in half/quarter rate. This sets up some default parameters which are then overridden by the driver (which manually configures things like slot timing at interface start time.) Although this is a copy-and-modify from the AR5212 HAL, I did peek at the reference HAL and the ath9k driver to see what they did. Ath9k in particular doesn't hard-code this - instead, their version of ar5416InitUserSettings() does all of the relevant math. TODO: * do the math, not hard code things! * fix the mac clock calculation for the AR9287; since it runs the MAC clock at a higher rate, requiring all the duration calculations to change; * Do a whole lot more validation for half/quarter rates. Obtained from: Qualcomm Atheros, Linux ath9k
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adrian
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ccf1eb95b9
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f769d7fc55
@ -62,6 +62,8 @@ static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
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uint16_t powerLimit);
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static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan);
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static void ar5416MarkPhyInactive(struct ath_hal *ah);
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static void ar5416SetIFSTiming(struct ath_hal *ah,
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const struct ieee80211_channel *chan);
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/*
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* Places the device in and out of reset and then places sane
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@ -310,11 +312,26 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
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ah->ah_resetTxQueue(ah, i);
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ar5416InitIMR(ah, opmode);
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ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);
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ar5416SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);
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ar5416InitQoS(ah);
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/* This may override the AR_DIAG_SW register */
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ar5416InitUserSettings(ah);
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/* XXX this won't work for AR9287! */
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if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) {
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ar5416SetIFSTiming(ah, chan);
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#if 0
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/*
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* AR5413?
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* Force window_length for 1/2 and 1/4 rate channels,
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* the ini file sets this to zero otherwise.
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*/
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OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
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AR_PHY_FRAME_CTL_WINLEN, 3);
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}
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#endif
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}
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if (AR_SREV_KIWI_13_OR_LATER(ah)) {
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/*
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* Enable ASYNC FIFO
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@ -2751,3 +2768,125 @@ ar5416MarkPhyInactive(struct ath_hal *ah)
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{
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OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
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}
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#define AR5416_IFS_SLOT_FULL_RATE_40 0x168 /* 9 us half, 40 MHz core clock (9*40) */
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#define AR5416_IFS_SLOT_HALF_RATE_40 0x104 /* 13 us half, 20 MHz core clock (13*20) */
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#define AR5416_IFS_SLOT_QUARTER_RATE_40 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */
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#define AR5416_IFS_EIFS_FULL_RATE_40 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */
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#define AR5416_IFS_EIFS_HALF_RATE_40 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */
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#define AR5416_IFS_EIFS_QUARTER_RATE_40 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */
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#define AR5416_IFS_SLOT_FULL_RATE_44 0x18c /* 9 us half, 44 MHz core clock (9*44) */
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#define AR5416_IFS_SLOT_HALF_RATE_44 0x11e /* 13 us half, 22 MHz core clock (13*22) */
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#define AR5416_IFS_SLOT_QUARTER_RATE_44 0xe7 /* 21 us quarter, 11 MHz core clock (21*11) */
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#define AR5416_IFS_EIFS_FULL_RATE_44 0xfd0 /* (74 + (2 * 9)) * 44MHz core clock */
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#define AR5416_IFS_EIFS_HALF_RATE_44 0xf0a /* (149 + (2 * 13)) * 22MHz core clock */
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#define AR5416_IFS_EIFS_QUARTER_RATE_44 0xe9c /* (298 + (2 * 21)) * 11MHz core clock */
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#define AR5416_INIT_USEC_40 40
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#define AR5416_HALF_RATE_USEC_40 19 /* ((40 / 2) - 1 ) */
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#define AR5416_QUARTER_RATE_USEC_40 9 /* ((40 / 4) - 1 ) */
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#define AR5416_INIT_USEC_44 44
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#define AR5416_HALF_RATE_USEC_44 21 /* ((44 / 2) - 1 ) */
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#define AR5416_QUARTER_RATE_USEC_44 10 /* ((44 / 4) - 1 ) */
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/* XXX What should these be for 40/44MHz clocks (and half/quarter) ? */
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#define AR5416_RX_NON_FULL_RATE_LATENCY 63
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#define AR5416_TX_HALF_RATE_LATENCY 108
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#define AR5416_TX_QUARTER_RATE_LATENCY 216
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/*
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* Adjust various register settings based on half/quarter rate clock setting.
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* This includes:
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*
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* + USEC, TX/RX latency,
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* + IFS params: slot, eifs, misc etc.
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*
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* TODO:
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*
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* + Verify which other registers need to be tweaked;
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* + Verify the behaviour of this for 5GHz fast and non-fast clock mode;
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* + This just plain won't work for long distance links - the coverage class
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* code isn't aware of the slot/ifs/ACK/RTS timeout values that need to
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* change;
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* + Verify whether the 32KHz USEC value needs to be kept for the 802.11n
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* series chips?
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* + Calculate/derive values for 2GHz, 5GHz, 5GHz fast clock
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*/
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static void
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ar5416SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan)
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{
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uint32_t txLat, rxLat, usec, slot, refClock, eifs, init_usec;
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int clk_44 = 0;
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HALASSERT(IEEE80211_IS_CHAN_HALF(chan) ||
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IEEE80211_IS_CHAN_QUARTER(chan));
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/* 2GHz and 5GHz fast clock - 44MHz; else 40MHz */
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if (IEEE80211_IS_CHAN_2GHZ(chan))
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clk_44 = 1;
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else if (IEEE80211_IS_CHAN_5GHZ(chan) &&
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IS_5GHZ_FAST_CLOCK_EN(ah, chan))
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clk_44 = 1;
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/* XXX does this need save/restoring for the 11n chips? */
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refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32;
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/*
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* XXX This really should calculate things, not use
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* hard coded values! Ew.
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*/
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if (IEEE80211_IS_CHAN_HALF(chan)) {
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if (clk_44) {
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slot = AR5416_IFS_SLOT_HALF_RATE_44;
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rxLat = AR5416_RX_NON_FULL_RATE_LATENCY <<
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AR5416_USEC_RX_LAT_S;
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txLat = AR5416_TX_HALF_RATE_LATENCY <<
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AR5416_USEC_TX_LAT_S;
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usec = AR5416_HALF_RATE_USEC_44;
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eifs = AR5416_IFS_EIFS_HALF_RATE_44;
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init_usec = AR5416_INIT_USEC_44 >> 1;
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} else {
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slot = AR5416_IFS_SLOT_HALF_RATE_40;
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rxLat = AR5416_RX_NON_FULL_RATE_LATENCY <<
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AR5416_USEC_RX_LAT_S;
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txLat = AR5416_TX_HALF_RATE_LATENCY <<
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AR5416_USEC_TX_LAT_S;
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usec = AR5416_HALF_RATE_USEC_40;
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eifs = AR5416_IFS_EIFS_HALF_RATE_40;
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init_usec = AR5416_INIT_USEC_40 >> 1;
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}
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} else { /* quarter rate */
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if (clk_44) {
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slot = AR5416_IFS_SLOT_QUARTER_RATE_44;
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rxLat = AR5416_RX_NON_FULL_RATE_LATENCY <<
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AR5416_USEC_RX_LAT_S;
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txLat = AR5416_TX_QUARTER_RATE_LATENCY <<
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AR5416_USEC_TX_LAT_S;
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usec = AR5416_QUARTER_RATE_USEC_44;
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eifs = AR5416_IFS_EIFS_QUARTER_RATE_44;
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init_usec = AR5416_INIT_USEC_44 >> 2;
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} else {
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slot = AR5416_IFS_SLOT_QUARTER_RATE_40;
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rxLat = AR5416_RX_NON_FULL_RATE_LATENCY <<
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AR5416_USEC_RX_LAT_S;
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txLat = AR5416_TX_QUARTER_RATE_LATENCY <<
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AR5416_USEC_TX_LAT_S;
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usec = AR5416_QUARTER_RATE_USEC_40;
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eifs = AR5416_IFS_EIFS_QUARTER_RATE_40;
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init_usec = AR5416_INIT_USEC_40 >> 2;
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}
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}
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/* XXX verify these! */
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OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat));
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OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);
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OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);
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OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC,
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AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec);
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}
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