Add userland access to at91 gpio functionality via ioctl calls. Also,
add the ability for userland to be notified of changes on gpio pins via a select(2)/read(2) interface. Change the interrupt handler from filtered to threaded. Because of the uiomove() calls in the new interface, change locking from standard mutex to sx. Add / restore the at91_gpio_high_z() function. Reviewed by: imp (long ago)
This commit is contained in:
ian
parent
581bf19e7b
commit
f7d5fae7ec
@ -1,5 +1,6 @@
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/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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* Copyright (C) 2012 Ian Lepore. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -35,22 +36,31 @@ __FBSDID("$FreeBSD$");
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/poll.h>
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#include <sys/rman.h>
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#include <sys/selinfo.h>
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#include <sys/sx.h>
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#include <sys/uio.h>
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#include <machine/at91_gpio.h>
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#include <machine/bus.h>
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#include <arm/at91/at91reg.h>
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#include <arm/at91/at91_pioreg.h>
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#include <arm/at91/at91_piovar.h>
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#define MAX_CHANGE 64
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struct at91_pio_softc
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{
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device_t dev; /* Myself */
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void *intrhand; /* Interrupt handle */
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struct resource *irq_res; /* IRQ resource */
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struct resource *mem_res; /* Memory resource */
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struct mtx sc_mtx; /* basically a perimeter lock */
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struct sx sc_mtx; /* basically a perimeter lock */
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struct cdev *cdev;
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struct selinfo selp;
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int buflen;
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uint8_t buf[MAX_CHANGE];
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int flags;
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#define OPENED 1
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};
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@ -69,14 +79,13 @@ WR4(struct at91_pio_softc *sc, bus_size_t off, uint32_t val)
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bus_write_4(sc->mem_res, off, val);
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}
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#define AT91_PIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
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#define AT91_PIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
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#define AT91_PIO_LOCK(_sc) sx_xlock(&(_sc)->sc_mtx)
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#define AT91_PIO_UNLOCK(_sc) sx_xunlock(&(_sc)->sc_mtx)
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#define AT91_PIO_LOCK_INIT(_sc) \
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mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
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"pio", MTX_SPIN)
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#define AT91_PIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define AT91_PIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
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#define AT91_PIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
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sx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev))
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#define AT91_PIO_LOCK_DESTROY(_sc) sx_destroy(&_sc->sc_mtx);
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#define AT91_PIO_ASSERT_LOCKED(_sc) sx_assert(&_sc->sc_mtx, SA_XLOCKED);
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#define AT91_PIO_ASSERT_UNLOCKED(_sc) sx_assert(&_sc->sc_mtx, SA_UNLOCKED);
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#define CDEV2SOFTC(dev) ((dev)->si_drv1)
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static devclass_t at91_pio_devclass;
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@ -86,7 +95,7 @@ static devclass_t at91_pio_devclass;
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static int at91_pio_probe(device_t dev);
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static int at91_pio_attach(device_t dev);
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static int at91_pio_detach(device_t dev);
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static int at91_pio_intr(void *);
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static void at91_pio_intr(void *);
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/* helper routines */
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static int at91_pio_activate(device_t dev);
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@ -95,6 +104,8 @@ static void at91_pio_deactivate(device_t dev);
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/* cdev routines */
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static d_open_t at91_pio_open;
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static d_close_t at91_pio_close;
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static d_read_t at91_pio_read;
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static d_poll_t at91_pio_poll;
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static d_ioctl_t at91_pio_ioctl;
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static struct cdevsw at91_pio_cdevsw =
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@ -102,6 +113,8 @@ static struct cdevsw at91_pio_cdevsw =
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.d_version = D_VERSION,
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.d_open = at91_pio_open,
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.d_close = at91_pio_close,
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.d_read = at91_pio_read,
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.d_poll = at91_pio_poll,
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.d_ioctl = at91_pio_ioctl
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};
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@ -154,7 +167,7 @@ at91_pio_attach(device_t dev)
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*/
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WR4(sc, PIO_IDR, 0xffffffff);
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err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC,
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at91_pio_intr, NULL, sc, &sc->intrhand);
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NULL, at91_pio_intr, sc, &sc->intrhand);
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if (err) {
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AT91_PIO_LOCK_DESTROY(sc);
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goto out;
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@ -213,7 +226,7 @@ at91_pio_deactivate(device_t dev)
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sc->intrhand = 0;
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bus_generic_detach(sc->dev);
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if (sc->mem_res)
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bus_release_resource(dev, SYS_RES_IOPORT,
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(sc->mem_res), sc->mem_res);
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sc->mem_res = 0;
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if (sc->irq_res)
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@ -222,22 +235,26 @@ at91_pio_deactivate(device_t dev)
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sc->irq_res = 0;
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}
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static int
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static void
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at91_pio_intr(void *xsc)
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{
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struct at91_pio_softc *sc = xsc;
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#if 0
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uint32_t status;
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int i;
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/* Reading the status also clears the interrupt. */
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status = RD4(sc, PIO_SR);
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if (status == 0)
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return;
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AT91_PIO_LOCK(sc);
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AT91_PIO_UNLOCK(sc);
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#endif
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wakeup(sc);
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return (FILTER_HANDLED);
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status = RD4(sc, PIO_ISR) & RD4(sc, PIO_IMR);
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if (status != 0) {
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AT91_PIO_LOCK(sc);
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for (i = 0; status != 0 && sc->buflen < MAX_CHANGE; ++i) {
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if (status & 1)
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sc->buf[sc->buflen++] = (uint8_t)i;
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status >>= 1;
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}
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AT91_PIO_UNLOCK(sc);
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wakeup(sc);
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selwakeup(&sc->selp);
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}
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}
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static int
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@ -249,9 +266,6 @@ at91_pio_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
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AT91_PIO_LOCK(sc);
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if (!(sc->flags & OPENED)) {
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sc->flags |= OPENED;
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#if 0
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/* Enable interrupts. */
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#endif
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}
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AT91_PIO_UNLOCK(sc);
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return (0);
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@ -265,19 +279,192 @@ at91_pio_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
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sc = CDEV2SOFTC(dev);
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AT91_PIO_LOCK(sc);
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sc->flags &= ~OPENED;
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#if 0
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/* Disable interrupts. */
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#endif
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AT91_PIO_UNLOCK(sc);
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return (0);
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}
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static int
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at91_pio_poll(struct cdev *dev, int events, struct thread *td)
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{
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struct at91_pio_softc *sc;
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int revents = 0;
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sc = CDEV2SOFTC(dev);
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AT91_PIO_LOCK(sc);
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if (events & (POLLIN | POLLRDNORM)) {
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if (sc->buflen != 0)
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revents |= events & (POLLIN | POLLRDNORM);
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else
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selrecord(td, &sc->selp);
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}
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AT91_PIO_UNLOCK(sc);
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return (revents);
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}
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static int
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at91_pio_read(struct cdev *dev, struct uio *uio, int flag)
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{
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struct at91_pio_softc *sc;
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int err, ret, len;
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sc = CDEV2SOFTC(dev);
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AT91_PIO_LOCK(sc);
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err = 0;
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ret = 0;
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while (uio->uio_resid) {
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while (sc->buflen == 0 && err == 0)
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err = msleep(sc, &sc->sc_mtx, PCATCH | PZERO, "prd", 0);
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if (err != 0)
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break;
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len = MIN(sc->buflen, uio->uio_resid);
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err = uiomove(sc->buf, len, uio);
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if (err != 0)
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break;
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/*
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* If we read the whole thing no datacopy is needed,
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* otherwise we move the data down.
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*/
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ret += len;
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if (sc->buflen == len)
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sc->buflen = 0;
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else {
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bcopy(sc->buf + len, sc->buf, sc->buflen - len);
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sc->buflen -= len;
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}
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/* If there's no data left, end the read. */
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if (sc->buflen == 0)
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break;
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}
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AT91_PIO_UNLOCK(sc);
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return (err);
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}
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static void
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at91_pio_bang32(struct at91_pio_softc *sc, uint32_t bits, uint32_t datapin,
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uint32_t clockpin)
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{
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int i;
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for (i = 0; i < 32; i++) {
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if (bits & 0x80000000)
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WR4(sc, PIO_SODR, datapin);
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else
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WR4(sc, PIO_CODR, datapin);
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bits <<= 1;
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WR4(sc, PIO_CODR, clockpin);
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WR4(sc, PIO_SODR, clockpin);
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}
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}
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static void
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at91_pio_bang(struct at91_pio_softc *sc, uint8_t bits, uint32_t bitcount,
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uint32_t datapin, uint32_t clockpin)
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{
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int i;
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for (i = 0; i < bitcount; i++) {
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if (bits & 0x80)
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WR4(sc, PIO_SODR, datapin);
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else
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WR4(sc, PIO_CODR, datapin);
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bits <<= 1;
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WR4(sc, PIO_CODR, clockpin);
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WR4(sc, PIO_SODR, clockpin);
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}
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}
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static int
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at91_pio_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
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struct thread *td)
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{
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struct at91_pio_softc *sc;
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struct at91_gpio_cfg *cfg;
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struct at91_gpio_info *info;
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struct at91_gpio_bang *bang;
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struct at91_gpio_bang_many *bangmany;
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uint32_t i, num;
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uint8_t many[1024], *walker;
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int err;
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int bitcount;
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return (ENXIO);
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sc = CDEV2SOFTC(dev);
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switch(cmd) {
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case AT91_GPIO_SET: /* turn bits on */
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WR4(sc, PIO_SODR, *(uint32_t *)data);
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return (0);
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case AT91_GPIO_CLR: /* turn bits off */
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WR4(sc, PIO_CODR, *(uint32_t *)data);
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return (0);
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case AT91_GPIO_READ: /* Get the status of input bits */
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*(uint32_t *)data = RD4(sc, PIO_PDSR);
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return (0);
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case AT91_GPIO_CFG: /* Configure AT91_GPIO pins */
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cfg = (struct at91_gpio_cfg *)data;
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if (cfg->cfgmask & AT91_GPIO_CFG_INPUT) {
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WR4(sc, PIO_OER, cfg->iomask & ~cfg->input);
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WR4(sc, PIO_ODR, cfg->iomask & cfg->input);
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}
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if (cfg->cfgmask & AT91_GPIO_CFG_HI_Z) {
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WR4(sc, PIO_MDDR, cfg->iomask & ~cfg->hi_z);
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WR4(sc, PIO_MDER, cfg->iomask & cfg->hi_z);
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}
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if (cfg->cfgmask & AT91_GPIO_CFG_PULLUP) {
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WR4(sc, PIO_PUDR, cfg->iomask & ~cfg->pullup);
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WR4(sc, PIO_PUER, cfg->iomask & cfg->pullup);
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}
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if (cfg->cfgmask & AT91_GPIO_CFG_GLITCH) {
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WR4(sc, PIO_IFDR, cfg->iomask & ~cfg->glitch);
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WR4(sc, PIO_IFER, cfg->iomask & cfg->glitch);
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}
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if (cfg->cfgmask & AT91_GPIO_CFG_GPIO) {
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WR4(sc, PIO_PDR, cfg->iomask & ~cfg->gpio);
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WR4(sc, PIO_PER, cfg->iomask & cfg->gpio);
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}
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if (cfg->cfgmask & AT91_GPIO_CFG_PERIPH) {
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WR4(sc, PIO_ASR, cfg->iomask & ~cfg->periph);
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WR4(sc, PIO_BSR, cfg->iomask & cfg->periph);
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}
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if (cfg->cfgmask & AT91_GPIO_CFG_INTR) {
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WR4(sc, PIO_IDR, cfg->iomask & ~cfg->intr);
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WR4(sc, PIO_IER, cfg->iomask & cfg->intr);
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}
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return (0);
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case AT91_GPIO_BANG:
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bang = (struct at91_gpio_bang *)data;
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at91_pio_bang32(sc, bang->bits, bang->datapin, bang->clockpin);
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return (0);
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case AT91_GPIO_BANG_MANY:
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bangmany = (struct at91_gpio_bang_many *)data;
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walker = (uint8_t *)bangmany->bits;
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bitcount = bangmany->numbits;
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while (bitcount > 0) {
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num = MIN((bitcount + 7) / 8, sizeof(many));
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err = copyin(walker, many, num);
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if (err)
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return err;
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for (i = 0; i < num && bitcount > 0; i++, bitcount -= 8)
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if (bitcount >= 8)
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at91_pio_bang(sc, many[i], 8, bangmany->datapin, bangmany->clockpin);
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else
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at91_pio_bang(sc, many[i], bitcount, bangmany->datapin, bangmany->clockpin);
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walker += num;
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}
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return (0);
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case AT91_GPIO_INFO: /* Learn about this device's AT91_GPIO bits */
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info = (struct at91_gpio_info *)data;
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info->output_status = RD4(sc, PIO_ODSR);
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info->input_status = RD4(sc, PIO_OSR);
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info->highz_status = RD4(sc, PIO_MDSR);
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info->pullup_status = RD4(sc, PIO_PUSR);
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info->glitch_status = RD4(sc, PIO_IFSR);
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info->enabled_status = RD4(sc, PIO_PSR);
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info->periph_status = RD4(sc, PIO_ABSR);
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info->intr_status = RD4(sc, PIO_IMR);
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memset(info->extra_status, 0, sizeof(info->extra_status));
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return (0);
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}
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return (ENOTTY);
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}
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/*
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@ -340,6 +527,17 @@ at91_pio_gpio_output(uint32_t pio, uint32_t output_enable_mask, int use_pullup)
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PIO[PIO_PUDR / 4] = output_enable_mask;
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}
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void
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at91_pio_gpio_high_z(uint32_t pio, uint32_t high_z_mask, int enable)
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{
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uint32_t *PIO = (uint32_t *)(AT91_BASE + pio);
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if (enable)
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PIO[PIO_MDER / 4] = high_z_mask;
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else
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PIO[PIO_MDDR / 4] = high_z_mask;
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}
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void
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at91_pio_gpio_set(uint32_t pio, uint32_t data_mask)
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{
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@ -36,6 +36,7 @@ void at91_pio_use_gpio(uint32_t pio, uint32_t gpio_mask);
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void at91_pio_gpio_input(uint32_t pio, uint32_t input_enable_mask);
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void at91_pio_gpio_output(uint32_t pio, uint32_t output_enable_mask,
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int use_pullup);
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void at91_pio_gpio_high_z(uint32_t pio, uint32_t high_z_mask, int enable);
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void at91_pio_gpio_set(uint32_t pio, uint32_t data_mask);
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void at91_pio_gpio_clear(uint32_t pio, uint32_t data_mask);
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uint8_t at91_pio_gpio_get(uint32_t pio, uint32_t data_mask);
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108
sys/arm/include/at91_gpio.h
Normal file
108
sys/arm/include/at91_gpio.h
Normal file
@ -0,0 +1,108 @@
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/*-
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* Copyright (C) 2006 M. Warner Losh. All rights reserved.
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* Copyright (C) 2012 Ian Lepore. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _ARM_AT91_GPIO_H
|
||||
#define _ARM_AT91_GPIO_H
|
||||
|
||||
#ifndef _KERNEL
|
||||
#include <sys/types.h>
|
||||
#endif
|
||||
#include <sys/ioccom.h>
|
||||
|
||||
/* Userland GPIO API for Atmel AT91 series SOC.
|
||||
*
|
||||
* Open /dev/pioN (where N is 0 for PIOA, 1 for PIOB, etc), and use ioctl(2)
|
||||
* calls to configure the pin(s) as needed.
|
||||
*
|
||||
* The userland interrupt support allows you to use read(2) and/or select(2) to
|
||||
* get notified of interrupts on PIO pins for which you enabled interrupt
|
||||
* notifications. Each time an interrupt occurs on a given pin, that pin number
|
||||
* is written into a buffer as a uint8_t. Thus, reading from /dev/pioN delivers
|
||||
* info on which interrupt(s) have occurred since the last read. You can also
|
||||
* use select() to block until an interrupt occurs (you still need to read() to
|
||||
* consume the interrupt number bytes from the buffer.)
|
||||
*/
|
||||
|
||||
struct at91_gpio_info
|
||||
{
|
||||
uint32_t output_status; /* Current state of output pins */
|
||||
uint32_t input_status; /* 1->out 0->in bitmask */
|
||||
uint32_t highz_status; /* 1->highz 0->driven bitmask */
|
||||
uint32_t pullup_status; /* 1->floating 0->pullup engaged */
|
||||
uint32_t glitch_status; /* 0-> no glitch filter 1->gf */
|
||||
uint32_t enabled_status; /* 1->used for pio 0->other */
|
||||
uint32_t periph_status; /* 0->A periph 1->B periph */
|
||||
uint32_t intr_status; /* 1-> ISR enabled, 0->disabled */
|
||||
uint32_t extra_status[8];/* Extra status info, device depend */
|
||||
};
|
||||
|
||||
struct at91_gpio_cfg
|
||||
{
|
||||
uint32_t cfgmask; /* which things change */
|
||||
#define AT91_GPIO_CFG_INPUT 0x01 /* configure input/output pins */
|
||||
#define AT91_GPIO_CFG_HI_Z 0x02 /* HiZ */
|
||||
#define AT91_GPIO_CFG_PULLUP 0x04 /* Enable/disable pullup resistors */
|
||||
#define AT91_GPIO_CFG_GLITCH 0x08 /* Glitch filtering */
|
||||
#define AT91_GPIO_CFG_GPIO 0x10 /* Use pin for PIO or peripheral */
|
||||
#define AT91_GPIO_CFG_PERIPH 0x20 /* Select which peripheral to use */
|
||||
#define AT91_GPIO_CFG_INTR 0x40 /* Select pin for interrupts */
|
||||
uint32_t iomask; /* Mask of bits to change */
|
||||
uint32_t input; /* or output */
|
||||
uint32_t hi_z; /* Disable output */
|
||||
uint32_t pullup; /* Enable pullup resistor */
|
||||
uint32_t glitch; /* Glitch filtering */
|
||||
uint32_t gpio; /* Enabled for PIO (1) or periph (0) */
|
||||
uint32_t periph; /* Select periph A (0) or periph B (1) */
|
||||
uint32_t intr; /* Enable interrupt (1), or not (0) */
|
||||
};
|
||||
|
||||
struct at91_gpio_bang
|
||||
{
|
||||
uint32_t clockpin; /* clock pin MASK */
|
||||
uint32_t datapin; /* Data pin MASK */
|
||||
uint32_t bits; /* bits to clock out (all 32) */
|
||||
};
|
||||
|
||||
struct at91_gpio_bang_many
|
||||
{
|
||||
uint32_t clockpin; /* clock pin MASK */
|
||||
uint32_t datapin; /* Data pin MASK */
|
||||
void *bits; /* bits to clock out */
|
||||
uint32_t numbits; /* Number of bits to clock out */
|
||||
};
|
||||
|
||||
#define AT91_GPIO_SET _IOW('g', 0, uint32_t) /* Turn bits on */
|
||||
#define AT91_GPIO_CLR _IOW('g', 1, uint32_t) /* Turn bits off */
|
||||
#define AT91_GPIO_READ _IOR('g', 2, uint32_t) /* Read input bit state */
|
||||
#define AT91_GPIO_INFO _IOR('g', 3, struct at91_gpio_info) /* State of pio cfg */
|
||||
#define AT91_GPIO_CFG _IOW('g', 4, struct at91_gpio_cfg) /* Configure pio */
|
||||
#define AT91_GPIO_BANG _IOW('g', 5, struct at91_gpio_bang) /* bit bang 32 bits */
|
||||
#define AT91_GPIO_BANG_MANY _IOW('g', 6, struct at91_gpio_bang_many)/* bit bang >32 bits */
|
||||
|
||||
#endif /* _ARM_AT91_GPIO_H */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user