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Fix E500 cache invalidation routines.

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When invalidating the i/d-cache we need to wait until the core complex is
really finished with the operation.

Obtained from:	Semihalf
This commit is contained in:
raj 2008-12-17 15:54:25 +00:00
parent 898a13418a
commit f811858422
1 changed files with 6 additions and 0 deletions
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6
sys/powerpc/booke/locore.S
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@ -411,6 +411,9 @@ ENTRY(dcache_inval)
isync
mtspr SPR_L1CSR0, %r3
isync
1: mfspr %r3, SPR_L1CSR0
andi. %r3, %r3, L1CSR0_DCFI
bne 1b
blr
ENTRY(dcache_disable)
@ -443,6 +446,9 @@ ENTRY(icache_inval)
isync
mtspr SPR_L1CSR1, %r3
isync
1: mfspr %r3, SPR_L1CSR1
andi. %r3, %r3, L1CSR1_ICFI
bne 1b
blr
ENTRY(icache_disable)