In xpt_set_transfer_settings(), force async if either the period or the

offset is set to 0.

Re-arrange the DT limiting code so that we don't end up setting the period
to 0xa if the user really wants async.  The previous behavior seemed to
confuse the aic(4) driver.

PR:		kern/22733
Reviewed by:	gibbs
This commit is contained in:
ken 2001-03-13 22:35:28 +00:00
parent 97b1e410af
commit f81f1df515

View File

@ -5836,22 +5836,24 @@ xpt_set_transfer_settings(struct ccb_trans_settings *cts, struct cam_ed *device,
cts->flags &= ~CCB_TRANS_TAG_ENB;
cts->flags |= cur_cts.flags & CCB_TRANS_TAG_ENB;
}
if (((device->flags & CAM_DEV_INQUIRY_DATA_VALID) != 0
&& (inq_data->flags & SID_Sync) == 0)
|| (cpi.hba_inquiry & PI_SDTR_ABLE) == 0) {
|| ((cpi.hba_inquiry & PI_SDTR_ABLE) == 0)
|| (cts->sync_offset == 0)
|| (cts->sync_period == 0)) {
/* Force async */
cts->sync_period = 0;
cts->sync_offset = 0;
}
/*
* Don't allow DT transmission rates if the
* device does not support it.
*/
if ((device->flags & CAM_DEV_INQUIRY_DATA_VALID) != 0
&& (inq_data->spi3data & SID_SPI_CLOCK_DT) == 0
&& cts->sync_period <= 0x9)
} else if ((device->flags & CAM_DEV_INQUIRY_DATA_VALID) != 0
&& (inq_data->spi3data & SID_SPI_CLOCK_DT) == 0
&& cts->sync_period <= 0x9) {
/*
* Don't allow DT transmission rates if the
* device does not support it.
*/
cts->sync_period = 0xa;
}
switch (cts->bus_width) {
case MSG_EXT_WDTR_BUS_32_BIT: