In xpt_set_transfer_settings(), force async if either the period or the
offset is set to 0. Re-arrange the DT limiting code so that we don't end up setting the period to 0xa if the user really wants async. The previous behavior seemed to confuse the aic(4) driver. PR: kern/22733 Reviewed by: gibbs
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@ -5836,22 +5836,24 @@ xpt_set_transfer_settings(struct ccb_trans_settings *cts, struct cam_ed *device,
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cts->flags &= ~CCB_TRANS_TAG_ENB;
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cts->flags |= cur_cts.flags & CCB_TRANS_TAG_ENB;
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}
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if (((device->flags & CAM_DEV_INQUIRY_DATA_VALID) != 0
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&& (inq_data->flags & SID_Sync) == 0)
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|| (cpi.hba_inquiry & PI_SDTR_ABLE) == 0) {
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|| ((cpi.hba_inquiry & PI_SDTR_ABLE) == 0)
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|| (cts->sync_offset == 0)
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|| (cts->sync_period == 0)) {
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/* Force async */
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cts->sync_period = 0;
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cts->sync_offset = 0;
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}
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/*
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* Don't allow DT transmission rates if the
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* device does not support it.
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*/
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if ((device->flags & CAM_DEV_INQUIRY_DATA_VALID) != 0
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&& (inq_data->spi3data & SID_SPI_CLOCK_DT) == 0
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&& cts->sync_period <= 0x9)
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} else if ((device->flags & CAM_DEV_INQUIRY_DATA_VALID) != 0
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&& (inq_data->spi3data & SID_SPI_CLOCK_DT) == 0
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&& cts->sync_period <= 0x9) {
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/*
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* Don't allow DT transmission rates if the
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* device does not support it.
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*/
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cts->sync_period = 0xa;
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}
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switch (cts->bus_width) {
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case MSG_EXT_WDTR_BUS_32_BIT:
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