Add Ingenic X1000 DTS files (unofficial).
This is based on JZ4780 due to missing original X1000 parts. Sponsored by: DARPA, AFRL
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42
sys/gnu/dts/mips/ingenic/canna.dts
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42
sys/gnu/dts/mips/ingenic/canna.dts
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@ -0,0 +1,42 @@
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/net/rfkill-regulator.h>
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#include "x1000.dtsi"
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/ {
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compatible = "ingenic,x1000";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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chosen {
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stdout-path = &uart2;
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x2000000>; /* 32 MiB at 0x0 */
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};
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};
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&ext {
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clock-frequency = <48000000>;
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};
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&msc0 {
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bus-width = <4>;
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max-frequency = <6000000>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pins_msc0_pa>;
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pins_uart2_dataplusflow>;
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};
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420
sys/gnu/dts/mips/ingenic/x1000.dtsi
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420
sys/gnu/dts/mips/ingenic/x1000.dtsi
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@ -0,0 +1,420 @@
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#include <dt-bindings/clock/jz4780-cgu.h>
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#include <dt-bindings/dma/jz4780-dma.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ingenic,x1000";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "ingenic,xburst";
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reg = <0>;
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};
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};
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cpuintc: cpuintc@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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intc: intc@10001000 {
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compatible = "ingenic,jz4780-intc";
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reg = <0x10001000 0x50>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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ext: ext {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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rtc: rtc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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cgu: jz4780-cgu@10000000 {
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compatible = "ingenic,jz4780-cgu";
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reg = <0x10000000 0x100>;
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clocks = <&ext>, <&rtc>;
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clock-names = "ext", "rtc";
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#clock-cells = <1>;
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <>;
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tcu@0x10002000 {
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compatible = "ingenic,jz4780-tcu";
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reg = <0x10002000 0x140>;
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interrupt-parent = <&intc>;
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interrupts = <27 26 25>;
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};
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watchdog: jz47xx-watchdog@0x10002000 {
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compatible = "ingenic,jz4780-watchdog";
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reg = <0x10002000 0x100>;
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clocks = <&rtc>;
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clock-names = "rtc";
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};
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rtcdev: rtcdev@10003000 {
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compatible = "ingenic,jz4780-rtc";
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reg = <0x10003000 0x4c>;
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interrupt-parent = <&intc>;
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interrupts = <32>;
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};
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i2s: i2s@10020000 {
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compatible = "ingenic,jz4780-i2s";
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reg = <0x10020000 0x94>;
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clocks = <&cgu JZ4780_CLK_AIC>, <&cgu JZ4780_CLK_I2SPLL>;
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clock-names = "aic", "i2s";
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dmas = <&dma 0 JZ4780_DMA_I2S0_RX 0xffffffff>, <&dma JZ4780_DMA_I2S0_TX 0 0xffffffff>;
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dma-names = "rx" , "tx";
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};
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codec: codec@100200a4 {
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compatible = "ingenic,jz4780-codec";
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reg = <0x100200a4 0x8>;
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clocks = <&cgu JZ4780_CLK_I2SPLL>;
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clock-names = "i2s";
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};
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pinctrl@0x10010000 {
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compatible = "ingenic,jz4780-pinctrl";
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reg = <0x10010000 0x600>;
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gpa: gpa {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <17>;
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ingenic,pull-ups = <0x3fffffff>;
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};
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gpb: gpb {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <16>;
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ingenic,pull-downs = <0x000f0c03>;
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ingenic,pull-ups = <0xfff0030c>;
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};
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gpc: gpc {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <15>;
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ingenic,pull-ups = <0xffffffff>;
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};
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gpd: gpd {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <14>;
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ingenic,pull-downs = <0x0000b000>;
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ingenic,pull-ups = <0xffff4fff>;
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};
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pincfg_nobias: nobias {
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bias-disable;
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};
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pincfg_pull_up: pull_up {
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bias-pull-up;
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};
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pincfg_pull_down: pull_down {
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bias-pull-down;
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};
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pinfunc_uart2: uart2 {
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pins_uart2_data: uart2-data {
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ingenic,pins = <&gpd 6 1 &pincfg_nobias /* rxd */
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&gpd 7 1 &pincfg_nobias>; /* txd */
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};
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pins_uart2_dataplusflow: uart2-dataplusflow {
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ingenic,pins = <&gpd 6 1 &pincfg_nobias /* rxd */
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&gpd 5 1 &pincfg_nobias /* cts */
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&gpd 4 1 &pincfg_nobias /* rts */
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&gpd 7 1 &pincfg_nobias>; /* txd */
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};
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};
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pinfunc_msc0: msc0 {
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pins_msc0_pa: msc0-pa {
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ingenic,pins = <&gpa 16 1 &pincfg_nobias /* d7 */
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&gpa 17 1 &pincfg_nobias /* d6 */
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&gpa 18 1 &pincfg_nobias /* d5 */
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&gpa 19 1 &pincfg_nobias /* d4 */
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&gpa 20 1 &pincfg_nobias /* d3 */
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&gpa 21 1 &pincfg_nobias /* d2 */
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&gpa 22 1 &pincfg_nobias /* d1 */
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&gpa 23 1 &pincfg_nobias /* d0 */
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&gpa 24 1 &pincfg_nobias /* clk */
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&gpa 25 1 &pincfg_nobias>; /* cmd */
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};
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};
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pinfunc_cim: cim {
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pins_cim: cim-pb {
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ingenic,pins = < /* Fill me. */ >;
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};
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};
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};
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uart0: serial@10030000 {
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compatible = "ingenic,jz4780-uart";
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reg = <0x10030000 0x100>;
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reg-shift = <2>;
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interrupt-parent = <&intc>;
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interrupts = <51>;
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status = "disabled";
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clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
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clock-names = "baud", "module";
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};
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uart1: serial@10031000 {
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compatible = "ingenic,jz4780-uart";
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reg = <0x10031000 0x100>;
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reg-shift = <2>;
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interrupt-parent = <&intc>;
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interrupts = <50>;
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status = "disabled";
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clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
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clock-names = "baud", "module";
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};
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uart2: serial@10032000 {
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compatible = "ingenic,jz4780-uart";
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reg = <0x10032000 0x100>;
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reg-shift = <2>;
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interrupt-parent = <&intc>;
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interrupts = <49>;
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clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
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clock-names = "baud", "module";
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};
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uart3: serial@10033000 {
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compatible = "ingenic,jz4780-uart";
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reg = <0x10033000 0x100>;
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reg-shift = <2>;
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interrupt-parent = <&intc>;
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interrupts = <48>;
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status = "disabled";
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clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
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clock-names = "baud", "module";
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};
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i2c0: i2c0@0x10050000 {
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compatible = "ingenic,jz4780-i2c";
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reg = <0x10050000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <60>;
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clocks = <&cgu JZ4780_CLK_SMB0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: i2c1@0x10051000 {
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compatible = "ingenic,jz4780-i2c";
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reg = <0x10051000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <59>;
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clocks = <&cgu JZ4780_CLK_SMB1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c2: i2c2@0x10052000 {
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compatible = "ingenic,jz4780-i2c";
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reg = <0x10052000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <58>;
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clocks = <&cgu JZ4780_CLK_SMB2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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lpcr: lcr@0x10000004 {
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compatible = "ingenic,jz4780-lcr";
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reg = <0x10000004 0x4>;
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regulators {
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vpu_power: VPU {
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};
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gpu_power: GPU {
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};
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gps_power: GPS {
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};
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};
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};
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};
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ahb2 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <>;
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lcd: jz4780-lcdk@0x13050000 {
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compatible = "ingenic,jz4780-lcd";
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reg = <0x13050000 0x1800>;
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clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
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clock-names = "lcd_clk", "lcd_pixclk";
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interrupt-parent = <&intc>;
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interrupts = <31>;
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};
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cim: jz4780-cim@0x13060000 {
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compatible = "ingenic,jz4780-cim";
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reg = <0x13060000 0x68>;
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reg-shift = <2>;
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interrupt-parent = <&intc>;
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interrupts = <30>;
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pinctrl-names = "default";
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pinctrl-0 = <&pins_cim>;
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clocks = <&cgu JZ4780_CLK_CIM>, <&cgu JZ4780_CLK_CIMMCLK>;
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clock-names = "cim", "module";
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};
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efuse: efuse@13540000 {
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compatible = "ingenic,jz4780-efuse";
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reg = <0x13540000 0xFF>;
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clocks = <&cgu JZ4780_CLK_AHB2>;
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clock-names = "bus_clk";
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};
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dma: dma@13420000 {
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compatible = "ingenic,jz4780-dma";
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reg = <0x13420000 0x10000>;
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interrupt-parent = <&intc>;
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interrupts = <10>;
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clocks = <&cgu JZ4780_CLK_PDMA>;
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#dma-cells = <3>;
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};
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msc0: msc@13450000 {
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compatible = "ingenic,jz4780-mmc";
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reg = <0x13450000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <37>;
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clocks = <&cgu JZ4780_CLK_MSC0>;
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clock-names = "mmc";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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cap-sdio-irq;
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dmas = <&dma JZ4780_DMA_MSC0_TX JZ4780_DMA_MSC0_RX 0xffffffff>;
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dma-names = "rx-tx";
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};
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msc1: msc@13460000 {
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compatible = "ingenic,jz4780-mmc";
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reg = <0x13460000 0x1000>;
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status = "disabled";
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interrupt-parent = <&intc>;
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interrupts = <36>;
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clocks = <&cgu JZ4780_CLK_MSC1>;
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clock-names = "mmc";
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cap-sd-highspeed;
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cap-mmc-highspeed;
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cap-sdio-irq;
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dmas = <&dma JZ4780_DMA_MSC1_TX JZ4780_DMA_MSC1_RX 0xffffffff>;
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dma-names = "rx-tx";
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};
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otg: jz4780-otg@0x13500000 {
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compatible = "ingenic,jz4780-otg";
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reg = <0x13500000 0x40000>;
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interrupt-parent = <&intc>;
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interrupts = <21>;
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clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_OTG1>;
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clock-names = "otg_phy", "otg1";
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};
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};
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};
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