Ensure interrupts are off while in {d,i}tlb_va_to_pa_sun4u().
I think this is necessary in order to make sure the workarounds in {d,i}tlb_get_data_sun4u() work correctly.
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@ -396,36 +396,44 @@ itlb_get_data_sun4u(int slot)
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static vm_offset_t
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dtlb_va_to_pa_sun4u(vm_offset_t va)
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{
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u_long reg;
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u_long pstate, reg;
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int i;
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pstate = rdpr(pstate);
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wrpr(pstate, pstate & ~PSTATE_IE, 0);
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for (i = 0; i < dtlb_slot_max; i++) {
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reg = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_TAG_READ_REG);
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if (TLB_TAR_VA(reg) != va)
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continue;
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reg = dtlb_get_data_sun4u(i);
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wrpr(pstate, pstate, 0);
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if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
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return ((reg & TD_PA_CH_MASK) >> TD_PA_SHIFT);
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return ((reg & TD_PA_SF_MASK) >> TD_PA_SHIFT);
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}
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wrpr(pstate, pstate, 0);
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return (-1);
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}
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static vm_offset_t
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itlb_va_to_pa_sun4u(vm_offset_t va)
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{
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u_long reg;
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u_long pstate, reg;
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int i;
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pstate = rdpr(pstate);
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wrpr(pstate, pstate & ~PSTATE_IE, 0);
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for (i = 0; i < itlb_slot_max; i++) {
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reg = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_TAG_READ_REG);
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if (TLB_TAR_VA(reg) != va)
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continue;
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reg = itlb_get_data_sun4u(i);
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wrpr(pstate, pstate, 0);
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if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
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return ((reg & TD_PA_CH_MASK) >> TD_PA_SHIFT);
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return ((reg & TD_PA_SF_MASK) >> TD_PA_SHIFT);
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}
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wrpr(pstate, pstate, 0);
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return (-1);
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}
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