Shuffle these initialisations to where they should be.
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@ -722,6 +722,13 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
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}
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#endif
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/*
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* Initial aggregation settings.
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*/
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sc->sc_hwq_limit = ATH_AGGR_MIN_QDEPTH;
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sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
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sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
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/*
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* Check if the hardware requires PCI register serialisation.
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* Some of the Owl based MACs require this.
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@ -1823,13 +1830,6 @@ ath_init(void *arg)
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*/
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sc->sc_beacons = 0;
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/*
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* Initial aggregation settings.
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*/
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sc->sc_hwq_limit = ATH_AGGR_MIN_QDEPTH;
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sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
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sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
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/*
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* Setup the hardware after reset: the key cache
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* is filled as needed and the receive engine is
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