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Make the Alternate {I,D} TLB vector code actually work for virtual

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addresses greater than 256M (the page size for region 6 and 7).
This commit is contained in:
Doug Rabson 2001-09-24 22:49:20 +00:00
parent 5312a8def5
commit f8c1540f3d
2 changed files with 4 additions and 4 deletions
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4
sys/ia64/ia64/exception.S
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@ -248,7 +248,7 @@ ia64_vector_table:
;;
dep r16=0,r16,50,14 // clear bits above PPN
;;
dep r16=r17,r17,0,12 // put pte bits in 0..11
dep r16=r17,r16,0,12 // put pte bits in 0..11
;;
itc.i r16
mov pr=r18,0x1ffff // restore predicates
@ -271,7 +271,7 @@ ia64_vector_table:
;;
dep r16=0,r16,50,14 // clear bits above PPN
;;
dep r16=r17,r17,0,12 // put pte bits in 0..11
dep r16=r17,r16,0,12 // put pte bits in 0..11
;;
itc.d r16
mov pr=r18,0x1ffff // restore predicates

4
sys/ia64/ia64/exception.s
View File

@ -248,7 +248,7 @@ ia64_vector_table:
;;
dep r16=0,r16,50,14 // clear bits above PPN
;;
dep r16=r17,r17,0,12 // put pte bits in 0..11
dep r16=r17,r16,0,12 // put pte bits in 0..11
;;
itc.i r16
mov pr=r18,0x1ffff // restore predicates
@ -271,7 +271,7 @@ ia64_vector_table:
;;
dep r16=0,r16,50,14 // clear bits above PPN
;;
dep r16=r17,r17,0,12 // put pte bits in 0..11
dep r16=r17,r16,0,12 // put pte bits in 0..11
;;
itc.d r16
mov pr=r18,0x1ffff // restore predicates