Fix some resource allocation peculiarities of the intpm device.
This commit is contained in:
Doug Rabson
parent
c864a1a7e8
commit
f8ef46e907
@ -60,6 +60,23 @@
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#include <machine/smp.h>
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#endif /* APIC_IO */
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struct pci_quirk {
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u_int32_t devid; /* Vendor/device of the card */
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int type;
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#define PCI_QUIRK_MAP_REG 1 /* PCI map register in wierd place */
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int arg1;
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int arg2;
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};
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struct pci_quirk pci_quirks[] = {
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/*
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* The Intel 82371AB has a map register at offset 0x90.
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*/
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{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
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{ 0 }
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};
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/* map register information */
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#define PCI_MAPMEM 0x01 /* memory map */
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#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
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@ -970,81 +987,100 @@ pci_memen(pcicfgregs *cfg)
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return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0);
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}
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/*
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* Add a resource based on a pci map register. Return 1 if the map
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* register is a 32bit map register or 2 if it is a 64bit register.
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*/
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static int
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pci_add_map(device_t dev, pcicfgregs* cfg, int reg)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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struct resource_list *rl = &dinfo->resources;
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u_int32_t map;
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u_int64_t base;
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u_int8_t ln2size;
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u_int8_t ln2range;
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u_int32_t testval;
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int type;
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map = pci_cfgread(cfg, reg, 4);
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if (map == 0 || map == 0xffffffff)
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return 1; /* skip invalid entry */
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pci_cfgwrite(cfg, reg, 0xffffffff, 4);
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testval = pci_cfgread(cfg, reg, 4);
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pci_cfgwrite(cfg, reg, map, 4);
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base = pci_mapbase(map);
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if (pci_maptype(map) & PCI_MAPMEM)
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type = SYS_RES_MEMORY;
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else
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type = SYS_RES_IOPORT;
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ln2size = pci_mapsize(testval);
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ln2range = pci_maprange(testval);
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if (ln2range == 64) {
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/* Read the other half of a 64bit map register */
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base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32;
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}
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#ifdef __alpha__
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/*
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* XXX: encode hose number in the base addr,
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* This will go away once the bus_space functions
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* can deal with multiple hoses
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*/
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if(cfg->hose){
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if (base & 0x80000000) {
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printf("base addr = 0x%x\n", base);
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printf("hacked addr = 0x%x\n",
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base | (cfg->hose << 31));
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panic("hose encoding hack would clobber base addr");
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}
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if (cfg->hose > 1)
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panic("only one hose supported!");
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base |= (cfg->hose << 31);
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}
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#endif
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if (type == SYS_RES_IOPORT && !pci_porten(cfg))
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return 1;
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if (type == SYS_RES_MEMORY && !pci_memen(cfg))
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return 1;
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resource_list_add(rl, type, reg,
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base, base + (1 << ln2size) - 1,
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(1 << ln2size));
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if (bootverbose) {
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printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
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reg, pci_maptype(base), ln2range,
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(unsigned int) base, ln2size);
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}
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return (ln2range == 64) ? 2 : 1;
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}
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static void
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pci_add_resources(device_t dev, pcicfgregs* cfg)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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struct resource_list *rl = &dinfo->resources;
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struct pci_quirk *q;
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int i;
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for (i = 0; i < cfg->nummaps; i++) {
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int reg = PCIR_MAPS + i*4;
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u_int32_t map;
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u_int64_t base;
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u_int8_t ln2size;
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u_int8_t ln2range;
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u_int32_t testval;
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int type;
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map = pci_cfgread(cfg, reg, 4);
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if (map == 0 || map == 0xffffffff)
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continue; /* skip invalid entry */
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pci_cfgwrite(cfg, reg, 0xffffffff, 4);
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testval = pci_cfgread(cfg, reg, 4);
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pci_cfgwrite(cfg, reg, map, 4);
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base = pci_mapbase(map);
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if (pci_maptype(map) & PCI_MAPMEM)
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type = SYS_RES_MEMORY;
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else
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type = SYS_RES_IOPORT;
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ln2size = pci_mapsize(testval);
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ln2range = pci_maprange(testval);
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if (ln2range == 64) {
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/* Read the other half of a 64bit map register */
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base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32;
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i++;
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}
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#ifdef __alpha__
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/*
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* XXX: encode hose number in the base addr,
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* This will go away once the bus_space functions
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* can deal with multiple hoses
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*/
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if(cfg->hose){
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if (base & 0x80000000) {
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printf("base addr = 0x%x\n", base);
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printf("hacked addr = 0x%x\n",
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base | (cfg->hose << 31));
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panic("hose encoding hack would clobber base addr");
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}
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if (cfg->hose > 1)
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panic("only one hose supported!");
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base |= (cfg->hose << 31);
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}
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#endif
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if (type == SYS_RES_IOPORT && !pci_porten(cfg))
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continue;
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if (type == SYS_RES_MEMORY && !pci_memen(cfg))
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continue;
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resource_list_add(rl, type, reg,
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base, base + (1 << ln2size) - 1,
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(1 << ln2size));
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if (bootverbose) {
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printf("\tmap[%d]: type %x, range %2d, base %08x, size %2d\n",
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i, pci_maptype(base), ln2range,
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(unsigned int) base, ln2size);
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}
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for (i = 0; i < cfg->nummaps;) {
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i += pci_add_map(dev, cfg, PCIR_MAPS + i*4);
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}
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for (q = &pci_quirks[0]; q->devid; q++) {
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if (q->devid == ((cfg->device << 16) | cfg->vendor)
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&& q->type == PCI_QUIRK_MAP_REG)
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pci_add_map(dev, cfg, q->arg1);
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}
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if (cfg->intline != 255)
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resource_list_add(rl, SYS_RES_IRQ, 0,
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cfg->intline, cfg->intline, 1);
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@ -1278,8 +1314,11 @@ static int
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pci_set_resource(device_t dev, device_t child, int type, int rid,
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u_long start, u_long count)
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{
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printf("pci_set_resource: PCI resources can not be changed\n");
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return EINVAL;
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struct pci_devinfo *dinfo = device_get_ivars(child);
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struct resource_list *rl = &dinfo->resources;
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resource_list_add(rl, type, rid, start, start + count - 1, count);
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return 0;
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}
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static int
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@ -1304,7 +1343,6 @@ static void
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pci_delete_resource(device_t dev, device_t child, int type, int rid)
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{
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printf("pci_set_resource: PCI resources can not be deleted\n");
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return EINVAL;
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}
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static u_int32_t
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@ -663,20 +663,8 @@ intpm_attach(device_t dev)
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}
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rid=PCI_BASE_ADDR_SMB;
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#if 0
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res=bus_alloc_resource(dev,SYS_RES_IOPORT,&rid,
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0,~0,1,RF_ACTIVE);
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if(res==NULL){
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device_printf(dev,"IO FAILED Trying Memory\n");
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res=bus_alloc_resource(dev,SYS_RES_MEMORY,&rid,0,~0,
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1,RF_ACTIVE);
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}
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#else
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/*Do as I tell!*/
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value=pci_read_config(dev,rid,4);
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res=bus_alloc_resource(dev,SYS_RES_IOPORT,&rid,value&(~1),
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(value&(~1))+256,256,RF_ACTIVE);
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#endif
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if(res==NULL){
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device_printf(dev,"Could not allocate Bus space\n");
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return ENXIO;
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@ -744,6 +732,7 @@ intpm_probe(device_t dev)
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++ep;
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if(ep->desc!=NULL){
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device_set_desc(dev,ep->desc);
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bus_set_resource(dev,SYS_RES_IRQ,0,9,1); /* XXX setup intr resource */
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return 0;
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}else{
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return ENXIO;
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178
sys/pci/pci.c
178
sys/pci/pci.c
@ -60,6 +60,23 @@
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#include <machine/smp.h>
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#endif /* APIC_IO */
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struct pci_quirk {
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u_int32_t devid; /* Vendor/device of the card */
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int type;
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#define PCI_QUIRK_MAP_REG 1 /* PCI map register in wierd place */
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int arg1;
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int arg2;
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};
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struct pci_quirk pci_quirks[] = {
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/*
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* The Intel 82371AB has a map register at offset 0x90.
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*/
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{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
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{ 0 }
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};
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/* map register information */
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#define PCI_MAPMEM 0x01 /* memory map */
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#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
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@ -970,81 +987,100 @@ pci_memen(pcicfgregs *cfg)
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return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0);
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}
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/*
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* Add a resource based on a pci map register. Return 1 if the map
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* register is a 32bit map register or 2 if it is a 64bit register.
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*/
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static int
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pci_add_map(device_t dev, pcicfgregs* cfg, int reg)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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struct resource_list *rl = &dinfo->resources;
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u_int32_t map;
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u_int64_t base;
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u_int8_t ln2size;
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u_int8_t ln2range;
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u_int32_t testval;
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int type;
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map = pci_cfgread(cfg, reg, 4);
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if (map == 0 || map == 0xffffffff)
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return 1; /* skip invalid entry */
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pci_cfgwrite(cfg, reg, 0xffffffff, 4);
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testval = pci_cfgread(cfg, reg, 4);
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pci_cfgwrite(cfg, reg, map, 4);
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base = pci_mapbase(map);
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if (pci_maptype(map) & PCI_MAPMEM)
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type = SYS_RES_MEMORY;
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else
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type = SYS_RES_IOPORT;
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ln2size = pci_mapsize(testval);
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ln2range = pci_maprange(testval);
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if (ln2range == 64) {
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/* Read the other half of a 64bit map register */
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base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32;
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}
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#ifdef __alpha__
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/*
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* XXX: encode hose number in the base addr,
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* This will go away once the bus_space functions
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* can deal with multiple hoses
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*/
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if(cfg->hose){
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if (base & 0x80000000) {
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printf("base addr = 0x%x\n", base);
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printf("hacked addr = 0x%x\n",
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base | (cfg->hose << 31));
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panic("hose encoding hack would clobber base addr");
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}
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if (cfg->hose > 1)
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panic("only one hose supported!");
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base |= (cfg->hose << 31);
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}
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#endif
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if (type == SYS_RES_IOPORT && !pci_porten(cfg))
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return 1;
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if (type == SYS_RES_MEMORY && !pci_memen(cfg))
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return 1;
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resource_list_add(rl, type, reg,
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base, base + (1 << ln2size) - 1,
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(1 << ln2size));
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if (bootverbose) {
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printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
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reg, pci_maptype(base), ln2range,
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(unsigned int) base, ln2size);
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}
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return (ln2range == 64) ? 2 : 1;
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}
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static void
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pci_add_resources(device_t dev, pcicfgregs* cfg)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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struct resource_list *rl = &dinfo->resources;
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struct pci_quirk *q;
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int i;
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for (i = 0; i < cfg->nummaps; i++) {
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int reg = PCIR_MAPS + i*4;
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u_int32_t map;
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u_int64_t base;
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u_int8_t ln2size;
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u_int8_t ln2range;
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u_int32_t testval;
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int type;
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map = pci_cfgread(cfg, reg, 4);
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if (map == 0 || map == 0xffffffff)
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continue; /* skip invalid entry */
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pci_cfgwrite(cfg, reg, 0xffffffff, 4);
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testval = pci_cfgread(cfg, reg, 4);
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pci_cfgwrite(cfg, reg, map, 4);
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base = pci_mapbase(map);
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if (pci_maptype(map) & PCI_MAPMEM)
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type = SYS_RES_MEMORY;
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else
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type = SYS_RES_IOPORT;
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ln2size = pci_mapsize(testval);
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ln2range = pci_maprange(testval);
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if (ln2range == 64) {
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/* Read the other half of a 64bit map register */
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base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32;
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i++;
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}
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#ifdef __alpha__
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/*
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* XXX: encode hose number in the base addr,
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* This will go away once the bus_space functions
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* can deal with multiple hoses
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*/
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if(cfg->hose){
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if (base & 0x80000000) {
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printf("base addr = 0x%x\n", base);
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printf("hacked addr = 0x%x\n",
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base | (cfg->hose << 31));
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panic("hose encoding hack would clobber base addr");
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}
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if (cfg->hose > 1)
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panic("only one hose supported!");
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base |= (cfg->hose << 31);
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}
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#endif
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if (type == SYS_RES_IOPORT && !pci_porten(cfg))
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continue;
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if (type == SYS_RES_MEMORY && !pci_memen(cfg))
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continue;
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resource_list_add(rl, type, reg,
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base, base + (1 << ln2size) - 1,
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(1 << ln2size));
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if (bootverbose) {
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printf("\tmap[%d]: type %x, range %2d, base %08x, size %2d\n",
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i, pci_maptype(base), ln2range,
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(unsigned int) base, ln2size);
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}
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for (i = 0; i < cfg->nummaps;) {
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i += pci_add_map(dev, cfg, PCIR_MAPS + i*4);
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}
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for (q = &pci_quirks[0]; q->devid; q++) {
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if (q->devid == ((cfg->device << 16) | cfg->vendor)
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&& q->type == PCI_QUIRK_MAP_REG)
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pci_add_map(dev, cfg, q->arg1);
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}
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if (cfg->intline != 255)
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resource_list_add(rl, SYS_RES_IRQ, 0,
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cfg->intline, cfg->intline, 1);
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@ -1278,8 +1314,11 @@ static int
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pci_set_resource(device_t dev, device_t child, int type, int rid,
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u_long start, u_long count)
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{
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printf("pci_set_resource: PCI resources can not be changed\n");
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return EINVAL;
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struct pci_devinfo *dinfo = device_get_ivars(child);
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struct resource_list *rl = &dinfo->resources;
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resource_list_add(rl, type, rid, start, start + count - 1, count);
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return 0;
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}
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static int
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@ -1304,7 +1343,6 @@ static void
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pci_delete_resource(device_t dev, device_t child, int type, int rid)
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{
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printf("pci_set_resource: PCI resources can not be deleted\n");
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return EINVAL;
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}
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static u_int32_t
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