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Fix from author of the driver:

Browse Source 
The i++ loop from 1..1000 is too small on very fast machines like
PII 450 MHz. Increasing the loop from 1..100000 lets the machine
access PHY. After this patch it's possible to use a SMC PCI card
on a HP Kayak XA series PC Workstation. Workaround until this fix
was to enable debugging in the driver (#define EPIC_DEBUG 1).

Without that patch you get an undefined state:
while true
do
ifconfig -a | grep status:
done
The status messages flaps between twwo values, but not
"connected".

Obtained from:	Ustimenko Semen <semen@iclub.nsu.ru>
This commit is contained in:
andreas 1999-03-09 17:30:12 +00:00
parent 68a0ddeab6
commit f90c5027c2
2 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
sys/dev/tx/if_tx.c
View File

@ -1,5 +1,5 @@
/* $OpenBSD: if_tx.c,v 1.3 1998/10/10 04:30:09 jason Exp $ */
/* $Id: if_tx.c,v 1.19 1998/12/09 01:12:18 eivind Exp $ */
/* $Id: if_tx.c,v 1.20 1998/12/14 06:32:56 dillon Exp $ */
/*-
* Copyright (c) 1997 Semen Ustimenko (semen@iclub.nsu.ru)
@ -1815,7 +1815,7 @@ epic_read_phy_register __P((
CSR_WRITE_4( sc, MIICTL, ((loc << 4) | 0x0601) );
for( i=0;i<0x1000;i++) if( !(CSR_READ_4( sc, MIICTL )&1) ) break;
for( i=0;i<0x100000;i++) if( !(CSR_READ_4( sc, MIICTL )&1) ) break;
return CSR_READ_4( sc, MIIDATA );
}
@ -1831,7 +1831,7 @@ epic_write_phy_register __P((
CSR_WRITE_4( sc, MIIDATA, val );
CSR_WRITE_4( sc, MIICTL, ((loc << 4) | 0x0602) );
for( i=0;i<0x1000;i++) if( !(CSR_READ_4( sc, MIICTL )&2) ) break;
for( i=0;i<0x100000;i++) if( !(CSR_READ_4( sc, MIICTL )&2) ) break;
return;
}

6
sys/pci/if_tx.c
View File

@ -1,5 +1,5 @@
/* $OpenBSD: if_tx.c,v 1.3 1998/10/10 04:30:09 jason Exp $ */
/* $Id: if_tx.c,v 1.19 1998/12/09 01:12:18 eivind Exp $ */
/* $Id: if_tx.c,v 1.20 1998/12/14 06:32:56 dillon Exp $ */
/*-
* Copyright (c) 1997 Semen Ustimenko (semen@iclub.nsu.ru)
@ -1815,7 +1815,7 @@ epic_read_phy_register __P((
CSR_WRITE_4( sc, MIICTL, ((loc << 4) | 0x0601) );
for( i=0;i<0x1000;i++) if( !(CSR_READ_4( sc, MIICTL )&1) ) break;
for( i=0;i<0x100000;i++) if( !(CSR_READ_4( sc, MIICTL )&1) ) break;
return CSR_READ_4( sc, MIIDATA );
}
@ -1831,7 +1831,7 @@ epic_write_phy_register __P((
CSR_WRITE_4( sc, MIIDATA, val );
CSR_WRITE_4( sc, MIICTL, ((loc << 4) | 0x0602) );
for( i=0;i<0x1000;i++) if( !(CSR_READ_4( sc, MIICTL )&2) ) break;
for( i=0;i<0x100000;i++) if( !(CSR_READ_4( sc, MIICTL )&2) ) break;
return;
}