[ath] add support for batching frames to the general TX queues.
It turns out the frame scheduling policies (eg DBA_GATED) operate on a single TX FIFO entry. ASAP scheduling is fine; those frames always go out. DBA-gated sets the TX queue ready when the DBA timer fires, which triggers a beacon transmit. Normally this is used for content-after-beacon queue (CABQ) work, which needs to burst out immediately after a beacon. (eg broadcast, multicast, etc frames.) This is a general policy that you can use for any queue, and Sam's TDMA code uses it. When DBA_GATED is used and something like say, an 11e TX burst window, it only operates on a single TX FIFO entry. If you have a single frame per TX FIFO entry and say, a 2.5ms long burst window (eg TDMA!) then it'll only burst a single frame every 2.5ms. If there's no gating (eg ASAP) then the burst window is fine, and multiple TX FIFO slots get used. The CABQ code does pack in a list of frames (ie, the whole cabq) but up until this commit, the normal TX queues didn't. It showed up when I started to debug TDMA on the AR9380 and later. This commit doesn't fix the TDMA case - that's still broken here, because all I'm doing here is allowing 'some' frames to be bursting, but I'm certainly not filling the whole TX FIFO slot entry with frames. Doing that 'properly' kind of requires me to take into account how long packets should take to transmit and say, doing 1.5 or something times that per TX FIFO slot, as if you partially transmit a slot, when it's next gated it'll just finish that TX FIFO slot, then not advance to the next one. Now, I /also/ think queuing a new packet restarts DMA, but you have to push new frames into the TX FIFO. I need to experiment some more with this because if it's really the case, I will be able to do TDMA support without the egregious hacks I have in my local tree. Sam's TDMA code for previous chips would just kick the TXE bit to push along DMA again, but we can't do that for EDMA chips - we /have/ to push a new frame into the TX FIFO to restart DMA. Ugh. Tested: * AR9380, STA mode * AR9380, hostap mode * AR9580, hostap mode Approved by: re (gjb)
This commit is contained in:
adrian
parent
ba73a9e651
commit
fa16c812f5
@ -138,14 +138,145 @@ MALLOC_DECLARE(M_ATHDEV);
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static void ath_edma_tx_processq(struct ath_softc *sc, int dosched);
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#ifdef ATH_DEBUG_ALQ
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static void
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ath_tx_alq_edma_push(struct ath_softc *sc, int txq, int nframes,
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int fifo_depth, int frame_cnt)
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{
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struct if_ath_alq_tx_fifo_push aq;
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aq.txq = htobe32(txq);
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aq.nframes = htobe32(nframes);
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aq.fifo_depth = htobe32(fifo_depth);
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aq.frame_cnt = htobe32(frame_cnt);
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if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TX_FIFO_PUSH,
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sizeof(aq),
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(const char *) &aq);
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}
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#endif /* ATH_DEBUG_ALQ */
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static void
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ath_tx_edma_push_staging_list(struct ath_softc *sc, struct ath_txq *txq,
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int limit)
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{
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struct ath_buf *bf, *bf_last;
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struct ath_buf *bfi, *bfp;
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int i, sqdepth;
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TAILQ_HEAD(axq_q_f_s, ath_buf) sq;
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ATH_TXQ_LOCK_ASSERT(txq);
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/*
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* Don't bother doing any work if it's full.
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*/
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if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH)
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return;
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if (TAILQ_EMPTY(&txq->axq_q))
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return;
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TAILQ_INIT(&sq);
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/*
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* First pass - walk sq, queue up to 'limit' entries,
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* subtract them from the staging queue.
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*/
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sqdepth = 0;
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for (i = 0; i < limit; i++) {
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/* Grab the head entry */
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bf = ATH_TXQ_FIRST(txq);
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if (bf == NULL)
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break;
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ATH_TXQ_REMOVE(txq, bf, bf_list);
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/* Queue it into our staging list */
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TAILQ_INSERT_TAIL(&sq, bf, bf_list);
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sqdepth++;
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}
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/*
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* Ok, so now we have a staging list of up to 'limit'
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* frames from the txq. Now let's wrap that up
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* into its own list and pass that to the hardware
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* as one FIFO entry.
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*/
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bf = TAILQ_FIRST(&sq);
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bf_last = TAILQ_LAST(&sq, axq_q_s);
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/*
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* Ok, so here's the gymnastics reqiured to make this
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* all sensible.
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*/
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/*
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* Tag the first/last buffer appropriately.
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*/
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bf->bf_flags |= ATH_BUF_FIFOPTR;
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bf_last->bf_flags |= ATH_BUF_FIFOEND;
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/*
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* Walk the descriptor list and link them appropriately.
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*/
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bfp = NULL;
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TAILQ_FOREACH(bfi, &sq, bf_list) {
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if (bfp != NULL) {
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ath_hal_settxdesclink(sc->sc_ah, bfp->bf_lastds,
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bfi->bf_daddr);
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}
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bfp = bfi;
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}
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i = 0;
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TAILQ_FOREACH(bfi, &sq, bf_list) {
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#ifdef ATH_DEBUG
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if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
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ath_printtxbuf(sc, bfi, txq->axq_qnum, i, 0);
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#endif/* ATH_DEBUG */
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#ifdef ATH_DEBUG_ALQ
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if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
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ath_tx_alq_post(sc, bfi);
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#endif /* ATH_DEBUG_ALQ */
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i++;
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}
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/*
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* We now need to push this set of frames onto the tail
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* of the FIFO queue. We don't adjust the aggregate
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* count, only the queue depth counter(s).
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* We also need to blank the link pointer now.
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*/
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TAILQ_CONCAT(&txq->fifo.axq_q, &sq, bf_list);
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/* Bump total queue tracking in FIFO queue */
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txq->fifo.axq_depth += sqdepth;
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/* Bump FIFO queue */
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txq->axq_fifo_depth++;
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DPRINTF(sc, ATH_DEBUG_XMIT,
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"%s: queued %d packets; depth=%d, fifo depth=%d\n",
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__func__, sqdepth, txq->fifo.axq_depth, txq->axq_fifo_depth);
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/* Push the first entry into the hardware */
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ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
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/* Push start on the DMA if it's not already started */
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ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
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#ifdef ATH_DEBUG_ALQ
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ath_tx_alq_edma_push(sc, txq->axq_qnum, sqdepth,
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txq->axq_fifo_depth,
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txq->fifo.axq_depth);
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#endif /* ATH_DEBUG_ALQ */
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}
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/*
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* Push some frames into the TX FIFO if we have space.
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*/
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static void
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ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq)
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{
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struct ath_buf *bf, *bf_last;
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int i = 0;
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ATH_TXQ_LOCK_ASSERT(txq);
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@ -153,64 +284,40 @@ ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq)
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__func__,
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txq->axq_qnum);
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TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
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if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH)
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break;
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/*
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* We have space in the FIFO - so let's push a frame
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* into it.
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*/
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/*
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* Remove it from the normal list
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*/
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ATH_TXQ_REMOVE(txq, bf, bf_list);
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/*
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* XXX for now, we only dequeue a frame at a time, so
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* that's only one buffer. Later on when we just
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* push this staging _list_ into the queue, we'll
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* set bf_last to the end pointer in the list.
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*/
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bf_last = bf;
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DPRINTF(sc, ATH_DEBUG_TX_PROC,
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"%s: Q%d: depth=%d; pushing %p->%p\n",
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__func__,
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txq->axq_qnum,
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txq->axq_fifo_depth,
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bf,
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bf_last);
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/*
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* Append it to the FIFO staging list
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*/
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ATH_TXQ_INSERT_TAIL(&txq->fifo, bf, bf_list);
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/*
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* Set fifo start / fifo end flags appropriately
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*
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*/
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bf->bf_flags |= ATH_BUF_FIFOPTR;
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bf_last->bf_flags |= ATH_BUF_FIFOEND;
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/*
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* Push _into_ the FIFO.
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*/
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ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
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#ifdef ATH_DEBUG
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if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
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ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0);
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#endif/* ATH_DEBUG */
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#ifdef ATH_DEBUG_ALQ
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if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
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ath_tx_alq_post(sc, bf);
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#endif /* ATH_DEBUG_ALQ */
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txq->axq_fifo_depth++;
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i++;
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}
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if (i > 0)
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ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
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/*
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* For now, push up to 4 frames per TX FIFO slot.
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* If more are in the hardware queue then they'll
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* get populated when we try to send another frame
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* or complete a frame - so at most there'll be
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* 32 non-AMPDU frames per TXQ.
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*
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* Note that the hardware staging queue will limit
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* how many frames in total we will have pushed into
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* here.
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*
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* Later on, we'll want to push less frames into
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* the TX FIFO since we don't want to necessarily
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* fill tens or hundreds of milliseconds of potential
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* frames.
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*
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* However, we need more frames right now because of
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* how the MAC implements the frame scheduling policy.
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* It only ungates a single FIFO entry at a time,
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* and will run that until CHNTIME expires or the
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* end of that FIFO entry descriptor list is reached.
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* So for TDMA we suffer a big performance penalty -
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* single TX FIFO entries mean the MAC only sends out
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* one frame per DBA event, which turned out on average
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* 6ms per TX frame.
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*
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* So, for aggregates it's okay - it'll push two at a
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* time and this will just do them more efficiently.
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* For non-aggregates it'll do 4 at a time, up to the
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* non-aggr limit (non_aggr, which is 32.) They should
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* be time based rather than a hard count, but I also
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* do need sleep.
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*/
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ath_tx_edma_push_staging_list(sc, txq, 4);
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}
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/*
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