Update arcmsr(4) to 1.50.00.00:
Add support for ARC-1886, NVMe/SAS/SATA controller. Many thanks to Areca for continuing to support FreeBSD. Submitted by: 黃清隆 <ching2048 areca com tw> MFC after: 2 weeks
This commit is contained in:
Xin LI
parent
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commit
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@ -24,7 +24,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd November 8, 2017
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.Dd October 15, 2020
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.Dt ARCMSR 4
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.Os
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.Sh NAME
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@ -153,6 +153,8 @@ ARC-1882
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ARC-1883
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.It
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ARC-1884
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.It
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ARC-1886
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.El
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.Sh FILES
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.Bl -tag -width ".Pa /dev/arcmsr?" -compact
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@ -81,6 +81,7 @@
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** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203
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** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884
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** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource
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** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller
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******************************************************************************************
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*/
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@ -138,7 +139,7 @@ __FBSDID("$FreeBSD$");
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#define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1);
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#define ARCMSR_DRIVER_VERSION "arcmsr version 1.40.00.01 2017-10-30"
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#define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.00 2020-09-30"
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#include <dev/arcmsr/arcmsr.h>
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/*
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**************************************************************************
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@ -176,6 +177,7 @@ static void arcmsr_polling_devmap(void *arg);
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static void arcmsr_srb_timeout(void *arg);
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static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
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static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb);
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static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb);
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static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb);
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#ifdef ARCMSR_DEBUG1
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static void arcmsr_dump_data(struct AdapterControlBlock *acb);
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@ -294,19 +296,20 @@ static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
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break;
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case ACB_ADAPTER_TYPE_C: {
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/* disable all outbound interrupt */
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intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */
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intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
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CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
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}
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break;
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case ACB_ADAPTER_TYPE_D: {
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/* disable all outbound interrupt */
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intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */
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intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */
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CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
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}
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break;
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case ACB_ADAPTER_TYPE_E: {
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case ACB_ADAPTER_TYPE_E:
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case ACB_ADAPTER_TYPE_F: {
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/* disable all outbound interrupt */
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intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */
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intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */
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CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE);
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}
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break;
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@ -352,7 +355,8 @@ static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t in
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acb->outbound_int_enable = mask;
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}
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break;
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case ACB_ADAPTER_TYPE_E: {
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case ACB_ADAPTER_TYPE_E:
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case ACB_ADAPTER_TYPE_F: {
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/* enable outbound Post Queue, outbound doorbell Interrupt */
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mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
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CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask);
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@ -577,7 +581,8 @@ static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
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arcmsr_flush_hbd_cache(acb);
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}
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break;
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case ACB_ADAPTER_TYPE_E: {
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case ACB_ADAPTER_TYPE_E:
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case ACB_ADAPTER_TYPE_F: {
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arcmsr_flush_hbe_cache(acb);
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}
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break;
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@ -733,7 +738,8 @@ static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
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arcmsr_abort_hbd_allcmd(acb);
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}
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break;
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case ACB_ADAPTER_TYPE_E: {
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case ACB_ADAPTER_TYPE_E:
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case ACB_ADAPTER_TYPE_F: {
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arcmsr_abort_hbe_allcmd(acb);
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}
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break;
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@ -844,6 +850,7 @@ static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t fl
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srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
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break;
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case ACB_ADAPTER_TYPE_E:
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case ACB_ADAPTER_TYPE_F:
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srb = acb->psrb_pool[flag_srb];
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break;
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default:
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@ -941,13 +948,14 @@ static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
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}
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}
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break;
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case ACB_ADAPTER_TYPE_D: {
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arcmsr_hbd_postqueue_isr(acb);
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}
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case ACB_ADAPTER_TYPE_D:
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arcmsr_hbd_postqueue_isr(acb);
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break;
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case ACB_ADAPTER_TYPE_E: {
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arcmsr_hbe_postqueue_isr(acb);
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}
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case ACB_ADAPTER_TYPE_E:
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arcmsr_hbe_postqueue_isr(acb);
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break;
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case ACB_ADAPTER_TYPE_F:
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arcmsr_hbf_postqueue_isr(acb);
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break;
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}
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}
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@ -1167,7 +1175,19 @@ static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandContr
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ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6));
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CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0);
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CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
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}
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}
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break;
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case ACB_ADAPTER_TYPE_F: {
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u_int32_t ccb_post_stamp, arc_cdb_size;
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if (srb->arc_cdb_size <= 0x300)
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arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1;
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else
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arc_cdb_size = (((srb->arc_cdb_size + 0xff) >> 8) + 2) << 1 | 1;
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ccb_post_stamp = (srb->smid | arc_cdb_size);
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CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0);
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CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp);
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}
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break;
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}
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}
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@ -1210,6 +1230,9 @@ static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
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qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
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}
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break;
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case ACB_ADAPTER_TYPE_F:
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qbuffer = (struct QBUFFER *)acb->message_rbuffer;
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break;
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}
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return(qbuffer);
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}
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@ -1252,6 +1275,9 @@ static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
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qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
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}
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break;
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case ACB_ADAPTER_TYPE_F:
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qbuffer = (struct QBUFFER *)acb->message_wbuffer;
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break;
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}
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return(qbuffer);
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}
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@ -1283,7 +1309,8 @@ static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
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CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
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}
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break;
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case ACB_ADAPTER_TYPE_E: {
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case ACB_ADAPTER_TYPE_E:
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case ACB_ADAPTER_TYPE_F: {
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/* let IOP know data has been read */
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acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
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CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
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@ -1331,7 +1358,8 @@ static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
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CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
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}
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break;
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case ACB_ADAPTER_TYPE_E: {
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case ACB_ADAPTER_TYPE_E:
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case ACB_ADAPTER_TYPE_F: {
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/*
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** push inbound doorbell tell iop, driver data write ok
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** and wait reply on next hwinterrupt for next Qbuffer post
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@ -1432,7 +1460,8 @@ static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
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arcmsr_stop_hbd_bgrb(acb);
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}
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break;
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case ACB_ADAPTER_TYPE_E: {
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case ACB_ADAPTER_TYPE_E:
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case ACB_ADAPTER_TYPE_F: {
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arcmsr_stop_hbe_bgrb(acb);
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}
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break;
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@ -1671,7 +1700,7 @@ static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int l
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union ccb *ccb;
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if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
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return;
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return;
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if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
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{
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xpt_free_ccb(ccb);
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@ -1760,8 +1789,16 @@ static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
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devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
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for (target = 0; target < 4; target++)
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{
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deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
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devicemap += 4;
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deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap);
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devicemap += 4;
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}
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break;
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case ACB_ADAPTER_TYPE_F:
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devicemap = ARCMSR_FW_DEVMAP_OFFSET;
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for (target = 0; target < 4; target++)
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{
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deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap];
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devicemap += 1;
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}
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break;
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}
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@ -1774,7 +1811,7 @@ static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
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** adapter posted CONFIG message
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** copy the new map, note if there are differences with the current map
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*/
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pDevMap = (u_int8_t *)&deviceMapCurrent[0];
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pDevMap = (u_int8_t *)&deviceMapCurrent[0];
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for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
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{
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if (*pDevMap != acb->device_map[target])
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@ -2002,7 +2039,7 @@ static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
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while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
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0, outbound_queueport)) != 0xFFFFFFFF) {
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/* check if command done with no error*/
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error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
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error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
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arcmsr_drain_donequeue(acb, flag_srb, error);
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} /*drain reply FIFO*/
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}
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@ -2031,7 +2068,7 @@ static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
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index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */
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phbbmu->doneq_index = index;
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/* check if command done with no error*/
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error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
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error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
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arcmsr_drain_donequeue(acb, flag_srb, error);
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} /*drain reply FIFO*/
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}
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@ -2049,7 +2086,7 @@ static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
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** areca cdb command done
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*****************************************************************************
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*/
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bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
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bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
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do {
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flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
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if (flag_srb == 0xFFFFFFFF)
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@ -2059,7 +2096,7 @@ static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
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arcmsr_drain_donequeue(acb, flag_srb, error);
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throttling++;
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if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
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CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
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CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
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throttling = 0;
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}
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} while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR);
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@ -2151,6 +2188,35 @@ static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb)
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acb->doneq_index = doneq_index;
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CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index);
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}
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static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb)
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{
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uint16_t error;
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uint32_t doneq_index;
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uint16_t cmdSMID;
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/*
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*****************************************************************************
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** areca cdb command done
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*****************************************************************************
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*/
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bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
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doneq_index = acb->doneq_index;
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while (1) {
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cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
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if (cmdSMID == 0xffff)
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break;
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error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
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arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error);
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acb->pCompletionQ[doneq_index].cmdSMID = 0xffff;
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doneq_index++;
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if (doneq_index >= acb->completionQ_entry)
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doneq_index = 0;
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}
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acb->doneq_index = doneq_index;
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CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index);
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}
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/*
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**********************************************************************
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**********************************************************************
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@ -2312,6 +2378,34 @@ static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb)
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host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status);
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} while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
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}
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static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb)
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{
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u_int32_t host_interrupt_status;
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/*
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*********************************************
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** check outbound intstatus
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*********************************************
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*/
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host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) &
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(ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
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ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
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if(!host_interrupt_status) {
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/*it must be share irq*/
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return;
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}
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do {
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/* MU doorbell interrupts*/
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if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
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arcmsr_hbe_doorbell_isr(acb);
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}
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/* MU post queue interrupts*/
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if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
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arcmsr_hbf_postqueue_isr(acb);
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}
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host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status);
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} while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
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}
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/*
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******************************************************************************
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******************************************************************************
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@ -2334,6 +2428,9 @@ static void arcmsr_interrupt(struct AdapterControlBlock *acb)
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case ACB_ADAPTER_TYPE_E:
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arcmsr_handle_hbe_isr(acb);
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break;
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case ACB_ADAPTER_TYPE_F:
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arcmsr_handle_hbf_isr(acb);
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break;
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default:
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printf("arcmsr%d: interrupt service,"
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" unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
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@ -2364,7 +2461,7 @@ static void arcmsr_polling_devmap(void *arg)
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CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
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break;
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case ACB_ADAPTER_TYPE_B: {
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||||
case ACB_ADAPTER_TYPE_B: {
|
||||
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
|
||||
WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
|
||||
}
|
||||
@ -2379,13 +2476,24 @@ static void arcmsr_polling_devmap(void *arg)
|
||||
CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
|
||||
break;
|
||||
|
||||
case ACB_ADAPTER_TYPE_E:
|
||||
case ACB_ADAPTER_TYPE_E:
|
||||
CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
|
||||
acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
|
||||
CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case ACB_ADAPTER_TYPE_F: {
|
||||
u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1);
|
||||
if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) ||
|
||||
(outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE))
|
||||
goto nxt6s;
|
||||
CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
|
||||
acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
|
||||
CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
|
||||
break;
|
||||
}
|
||||
}
|
||||
nxt6s:
|
||||
if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
|
||||
{
|
||||
callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */
|
||||
@ -3311,6 +3419,7 @@ static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
|
||||
arcmsr_start_hbd_bgrb(acb);
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_E:
|
||||
case ACB_ADAPTER_TYPE_F:
|
||||
arcmsr_start_hbe_bgrb(acb);
|
||||
break;
|
||||
}
|
||||
@ -3452,7 +3561,7 @@ static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct C
|
||||
break;
|
||||
}
|
||||
if (acb->srboutstandingcount == 0) {
|
||||
break;
|
||||
break;
|
||||
}
|
||||
goto polling_ccb_retry;
|
||||
}
|
||||
@ -3555,12 +3664,12 @@ static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct C
|
||||
break;/*chip FIFO no ccb for completion already*/
|
||||
} else {
|
||||
UDELAY(25000);
|
||||
if ((poll_count > 100) && (poll_srb != NULL)) {
|
||||
if ((poll_count > 100) && (poll_srb != NULL)) {
|
||||
break;
|
||||
}
|
||||
if (acb->srboutstandingcount == 0) {
|
||||
break;
|
||||
}
|
||||
if (acb->srboutstandingcount == 0) {
|
||||
break;
|
||||
}
|
||||
goto polling_ccb_retry;
|
||||
}
|
||||
}
|
||||
@ -3596,25 +3705,21 @@ static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct C
|
||||
static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
|
||||
{
|
||||
switch (acb->adapter_type) {
|
||||
case ACB_ADAPTER_TYPE_A: {
|
||||
arcmsr_polling_hba_srbdone(acb, poll_srb);
|
||||
}
|
||||
case ACB_ADAPTER_TYPE_A:
|
||||
arcmsr_polling_hba_srbdone(acb, poll_srb);
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_B: {
|
||||
arcmsr_polling_hbb_srbdone(acb, poll_srb);
|
||||
}
|
||||
case ACB_ADAPTER_TYPE_B:
|
||||
arcmsr_polling_hbb_srbdone(acb, poll_srb);
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_C: {
|
||||
arcmsr_polling_hbc_srbdone(acb, poll_srb);
|
||||
}
|
||||
case ACB_ADAPTER_TYPE_C:
|
||||
arcmsr_polling_hbc_srbdone(acb, poll_srb);
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_D: {
|
||||
arcmsr_polling_hbd_srbdone(acb, poll_srb);
|
||||
}
|
||||
case ACB_ADAPTER_TYPE_D:
|
||||
arcmsr_polling_hbd_srbdone(acb, poll_srb);
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_E: {
|
||||
arcmsr_polling_hbe_srbdone(acb, poll_srb);
|
||||
}
|
||||
case ACB_ADAPTER_TYPE_E:
|
||||
case ACB_ADAPTER_TYPE_F:
|
||||
arcmsr_polling_hbe_srbdone(acb, poll_srb);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -3874,28 +3979,80 @@ static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb)
|
||||
**********************************************************************
|
||||
**********************************************************************
|
||||
*/
|
||||
static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb)
|
||||
{
|
||||
u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model;
|
||||
u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version;
|
||||
u_int32_t *acb_device_map = (u_int32_t *)acb->device_map;
|
||||
size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/
|
||||
size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/
|
||||
size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET;
|
||||
int i;
|
||||
|
||||
CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
|
||||
acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
|
||||
CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
|
||||
if(!arcmsr_hbe_wait_msgint_ready(acb))
|
||||
printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
|
||||
|
||||
i = 0;
|
||||
while(i < 2) {
|
||||
*acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model];
|
||||
/* 8 bytes firm_model, 15, 60-67*/
|
||||
acb_firm_model++;
|
||||
iop_firm_model++;
|
||||
i++;
|
||||
}
|
||||
i = 0;
|
||||
while(i < 4) {
|
||||
*acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version];
|
||||
/* 16 bytes firm_version, 17, 68-83*/
|
||||
acb_firm_version++;
|
||||
iop_firm_version++;
|
||||
i++;
|
||||
}
|
||||
i = 0;
|
||||
while(i < 4) {
|
||||
*acb_device_map = acb->msgcode_rwbuffer[iop_device_map];
|
||||
acb_device_map++;
|
||||
iop_device_map++;
|
||||
i++;
|
||||
}
|
||||
printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
|
||||
acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/
|
||||
acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/
|
||||
acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/
|
||||
acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/
|
||||
acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/
|
||||
if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
|
||||
acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
|
||||
else
|
||||
acb->maxOutstanding = acb->firm_numbers_queue - 1;
|
||||
}
|
||||
/*
|
||||
**********************************************************************
|
||||
**********************************************************************
|
||||
*/
|
||||
static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
|
||||
{
|
||||
switch (acb->adapter_type) {
|
||||
case ACB_ADAPTER_TYPE_A: {
|
||||
arcmsr_get_hba_config(acb);
|
||||
}
|
||||
case ACB_ADAPTER_TYPE_A:
|
||||
arcmsr_get_hba_config(acb);
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_B: {
|
||||
arcmsr_get_hbb_config(acb);
|
||||
}
|
||||
case ACB_ADAPTER_TYPE_B:
|
||||
arcmsr_get_hbb_config(acb);
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_C: {
|
||||
arcmsr_get_hbc_config(acb);
|
||||
}
|
||||
case ACB_ADAPTER_TYPE_C:
|
||||
arcmsr_get_hbc_config(acb);
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_D: {
|
||||
arcmsr_get_hbd_config(acb);
|
||||
}
|
||||
case ACB_ADAPTER_TYPE_D:
|
||||
arcmsr_get_hbd_config(acb);
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_E: {
|
||||
arcmsr_get_hbe_config(acb);
|
||||
}
|
||||
case ACB_ADAPTER_TYPE_E:
|
||||
arcmsr_get_hbe_config(acb);
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_F:
|
||||
arcmsr_get_hbf_config(acb);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -3958,7 +4115,8 @@ static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
|
||||
}
|
||||
}
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_E: {
|
||||
case ACB_ADAPTER_TYPE_E:
|
||||
case ACB_ADAPTER_TYPE_F: {
|
||||
while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0)
|
||||
{
|
||||
if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */
|
||||
@ -4011,7 +4169,8 @@ static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
|
||||
CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
|
||||
}
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_E: {
|
||||
case ACB_ADAPTER_TYPE_E:
|
||||
case ACB_ADAPTER_TYPE_F: {
|
||||
/* empty doorbell Qbuffer if door bell ringed */
|
||||
acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell);
|
||||
CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */
|
||||
@ -4146,6 +4305,27 @@ static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
|
||||
}
|
||||
}
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_F: {
|
||||
u_int32_t cdb_phyaddr_lo32;
|
||||
cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb);
|
||||
acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG;
|
||||
acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886;
|
||||
acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32;
|
||||
acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32;
|
||||
acb->msgcode_rwbuffer[4] = SRB_SIZE;
|
||||
cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE;
|
||||
acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32;
|
||||
acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32;
|
||||
acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE;
|
||||
CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
|
||||
acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
|
||||
CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell);
|
||||
if(!arcmsr_hbe_wait_msgint_ready(acb)) {
|
||||
printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
return (TRUE);
|
||||
}
|
||||
@ -4209,7 +4389,7 @@ static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, in
|
||||
return;
|
||||
}
|
||||
if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)
|
||||
|| (acb->adapter_type == ACB_ADAPTER_TYPE_E))
|
||||
|| (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F))
|
||||
{
|
||||
srb_tmp->cdb_phyaddr_low = srb_phyaddr;
|
||||
srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
|
||||
@ -4224,6 +4404,15 @@ static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, in
|
||||
}
|
||||
if (acb->adapter_type == ACB_ADAPTER_TYPE_E)
|
||||
acb->pCompletionQ = (pCompletion_Q)srb_tmp;
|
||||
else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) {
|
||||
acb->pCompletionQ = (pCompletion_Q)srb_tmp;
|
||||
acb->completeQ_phys = srb_phyaddr;
|
||||
memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE);
|
||||
acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE);
|
||||
acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100);
|
||||
acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200);
|
||||
memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE);
|
||||
}
|
||||
acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
|
||||
}
|
||||
/*
|
||||
@ -4299,6 +4488,13 @@ static u_int32_t arcmsr_initialize(device_t dev)
|
||||
max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE;
|
||||
acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
|
||||
break;
|
||||
case PCIDevVenIDARC1886_:
|
||||
case PCIDevVenIDARC1886:
|
||||
acb->adapter_type = ACB_ADAPTER_TYPE_F;
|
||||
acb->adapter_bus_speed = ACB_BUS_SPEED_12G;
|
||||
max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE;
|
||||
acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ);
|
||||
break;
|
||||
case PCIDevVenIDARC1214: {
|
||||
acb->adapter_type = ACB_ADAPTER_TYPE_D;
|
||||
acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
|
||||
@ -4513,7 +4709,7 @@ static u_int32_t arcmsr_initialize(device_t dev)
|
||||
u_int32_t rid0 = PCIR_BAR(1);
|
||||
vm_offset_t mem_base0;
|
||||
|
||||
acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
|
||||
acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
|
||||
if(acb->sys_res_arcmsr[0] == NULL) {
|
||||
arcmsr_free_resource(acb);
|
||||
printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
|
||||
@ -4541,7 +4737,7 @@ static u_int32_t arcmsr_initialize(device_t dev)
|
||||
u_int32_t rid0 = PCIR_BAR(0);
|
||||
vm_offset_t mem_base0;
|
||||
|
||||
acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE);
|
||||
acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
|
||||
if(acb->sys_res_arcmsr[0] == NULL) {
|
||||
arcmsr_free_resource(acb);
|
||||
printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
|
||||
@ -4598,6 +4794,44 @@ static u_int32_t arcmsr_initialize(device_t dev)
|
||||
CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
|
||||
}
|
||||
break;
|
||||
case ACB_ADAPTER_TYPE_F: {
|
||||
u_int32_t rid0 = PCIR_BAR(0);
|
||||
vm_offset_t mem_base0;
|
||||
unsigned long host_buffer_dma;
|
||||
|
||||
acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE);
|
||||
if(acb->sys_res_arcmsr[0] == NULL) {
|
||||
arcmsr_free_resource(acb);
|
||||
printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
|
||||
return ENOMEM;
|
||||
}
|
||||
if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
|
||||
arcmsr_free_resource(acb);
|
||||
printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
|
||||
return ENXIO;
|
||||
}
|
||||
mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
|
||||
if(mem_base0 == 0) {
|
||||
arcmsr_free_resource(acb);
|
||||
printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
|
||||
return ENXIO;
|
||||
}
|
||||
acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
|
||||
acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
|
||||
acb->pmu = (struct MessageUnit_UNION *)mem_base0;
|
||||
acb->doneq_index = 0;
|
||||
acb->in_doorbell = 0;
|
||||
acb->out_doorbell = 0;
|
||||
acb->rid[0] = rid0;
|
||||
arcmsr_wait_firmware_ready(acb);
|
||||
CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/
|
||||
CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */
|
||||
host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE;
|
||||
CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */
|
||||
CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */
|
||||
CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */
|
||||
}
|
||||
break;
|
||||
}
|
||||
if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
|
||||
arcmsr_free_resource(acb);
|
||||
@ -4802,6 +5036,10 @@ static int arcmsr_probe(device_t dev)
|
||||
case PCIDevVenIDARC1884:
|
||||
type = "SAS 12G";
|
||||
break;
|
||||
case PCIDevVenIDARC1886_:
|
||||
case PCIDevVenIDARC1886:
|
||||
type = "NVME,SAS-12G,SATA-6G";
|
||||
break;
|
||||
case PCIDevVenIDARC1214:
|
||||
case PCIDevVenIDARC1203:
|
||||
type = "SATA 6G";
|
||||
|
||||
@ -150,6 +150,8 @@ typedef struct mtx arcmsr_lock_t;
|
||||
#define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */
|
||||
#define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */
|
||||
#define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */
|
||||
#define PCIDevVenIDARC1886_ 0x188917D3 /* Vendor Device ID */
|
||||
#define PCIDevVenIDARC1886 0x188A17D3 /* Vendor Device ID */
|
||||
|
||||
#ifndef PCIR_BARS
|
||||
#define PCIR_BARS 0x10
|
||||
@ -458,7 +460,7 @@ struct CMD_MESSAGE_FIELD {
|
||||
|
||||
/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
|
||||
#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000
|
||||
/*
|
||||
/*
|
||||
*******************************************************************************
|
||||
** SPEC. for Areca HBE adapter
|
||||
*******************************************************************************
|
||||
@ -478,9 +480,23 @@ struct CMD_MESSAGE_FIELD {
|
||||
/* ARC-1884 doorbell sync */
|
||||
#define ARCMSR_HBEMU_DOORBELL_SYNC 0x100
|
||||
#define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004
|
||||
/*
|
||||
*******************************************************************************
|
||||
** SPEC. for Areca HBF adapter
|
||||
*******************************************************************************
|
||||
*/
|
||||
#define ARCMSR_SIGNATURE_1886 0x188617D3
|
||||
// Doorbell and interrupt definition are same as Type E adapter
|
||||
/* ARC-1886 doorbell sync */
|
||||
#define ARCMSR_HBFMU_DOORBELL_SYNC 0x100
|
||||
//set host rw buffer physical address at inbound message 0, 1 (low,high)
|
||||
#define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300
|
||||
#define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000
|
||||
#define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000
|
||||
|
||||
/*
|
||||
*********************************************************************
|
||||
** Message Unit structure
|
||||
** Messaging Unit (MU) of Type A processor
|
||||
*********************************************************************
|
||||
*/
|
||||
struct HBA_MessageUnit
|
||||
@ -544,7 +560,7 @@ struct HBB_RWBUFFER
|
||||
};
|
||||
/*
|
||||
*********************************************************************
|
||||
**
|
||||
** Messaging Unit (MU) of Type B processor(MARVEL)
|
||||
*********************************************************************
|
||||
*/
|
||||
struct HBB_MessageUnit
|
||||
@ -563,7 +579,7 @@ struct HBB_MessageUnit
|
||||
|
||||
/*
|
||||
*********************************************************************
|
||||
**
|
||||
** Messaging Unit (MU) of Type C processor(LSI)
|
||||
*********************************************************************
|
||||
*/
|
||||
struct HBC_MessageUnit {
|
||||
@ -638,7 +654,7 @@ struct HBC_MessageUnit {
|
||||
};
|
||||
/*
|
||||
*********************************************************************
|
||||
**
|
||||
** Messaging Unit (MU) of Type D processor
|
||||
*********************************************************************
|
||||
*/
|
||||
struct InBound_SRB {
|
||||
@ -707,7 +723,7 @@ struct HBD_MessageUnit0 {
|
||||
};
|
||||
/*
|
||||
*********************************************************************
|
||||
**
|
||||
** Messaging Unit (MU) of Type E processor(LSI)
|
||||
*********************************************************************
|
||||
*/
|
||||
struct HBE_MessageUnit {
|
||||
@ -783,6 +799,80 @@ struct HBE_MessageUnit {
|
||||
u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/
|
||||
};
|
||||
|
||||
/*
|
||||
*********************************************************************
|
||||
** Messaging Unit (MU) of Type F processor(LSI)
|
||||
*********************************************************************
|
||||
*/
|
||||
struct HBF_MessageUnit {
|
||||
u_int32_t iobound_doorbell; /*0000 0003*/
|
||||
u_int32_t write_sequence_3xxx; /*0004 0007*/
|
||||
u_int32_t host_diagnostic_3xxx; /*0008 000B*/
|
||||
u_int32_t posted_outbound_doorbell; /*000C 000F*/
|
||||
u_int32_t master_error_attribute; /*0010 0013*/
|
||||
u_int32_t master_error_address_low; /*0014 0017*/
|
||||
u_int32_t master_error_address_high; /*0018 001B*/
|
||||
u_int32_t hcb_size; /*001C 001F*/
|
||||
u_int32_t inbound_doorbell; /*0020 0023*/
|
||||
u_int32_t diagnostic_rw_data; /*0024 0027*/
|
||||
u_int32_t diagnostic_rw_address_low; /*0028 002B*/
|
||||
u_int32_t diagnostic_rw_address_high; /*002C 002F*/
|
||||
u_int32_t host_int_status; /*0030 0033 host interrupt status*/
|
||||
u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/
|
||||
u_int32_t dcr_data; /*0038 003B*/
|
||||
u_int32_t dcr_address; /*003C 003F*/
|
||||
u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
|
||||
u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
|
||||
u_int32_t hcb_pci_address_low; /*0048 004B*/
|
||||
u_int32_t hcb_pci_address_high; /*004C 004F*/
|
||||
u_int32_t iop_int_status; /*0050 0053*/
|
||||
u_int32_t iop_int_mask; /*0054 0057*/
|
||||
u_int32_t iop_inbound_queue_port; /*0058 005B*/
|
||||
u_int32_t iop_outbound_queue_port; /*005C 005F*/
|
||||
u_int32_t inbound_free_list_index; /*0060 0063*/
|
||||
u_int32_t inbound_post_list_index; /*0064 0067*/
|
||||
u_int32_t reply_post_producer_index; /*0068 006B*/
|
||||
u_int32_t reply_post_consumer_index; /*006C 006F*/
|
||||
u_int32_t inbound_doorbell_clear; /*0070 0073*/
|
||||
u_int32_t i2o_message_unit_control; /*0074 0077*/
|
||||
u_int32_t last_used_message_source_address_low; /*0078 007B*/
|
||||
u_int32_t last_used_message_source_address_high; /*007C 007F*/
|
||||
u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/
|
||||
u_int32_t message_dest_address_index; /*0090 0093*/
|
||||
u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
|
||||
u_int32_t utility_A_int_counter_timer; /*0098 009B*/
|
||||
u_int32_t outbound_doorbell; /*009C 009F*/
|
||||
u_int32_t outbound_doorbell_clear; /*00A0 00A3*/
|
||||
u_int32_t message_source_address_index; /*00A4 00A7*/
|
||||
u_int32_t message_done_queue_index; /*00A8 00AB*/
|
||||
u_int32_t reserved0; /*00AC 00AF*/
|
||||
u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/
|
||||
u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/
|
||||
u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/
|
||||
u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/
|
||||
u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/
|
||||
u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/
|
||||
u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/
|
||||
u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/
|
||||
u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/
|
||||
u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/
|
||||
u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/
|
||||
u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/
|
||||
u_int32_t message_dest_queue_port_low; /*00E0 00E3*/
|
||||
u_int32_t message_dest_queue_port_high; /*00E4 00E7*/
|
||||
u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/
|
||||
u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/
|
||||
u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/
|
||||
u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/
|
||||
u_int32_t host_diagnostic; /*00F8 00FB*/
|
||||
u_int32_t write_sequence; /*00FC 00FF*/
|
||||
u_int32_t reserved1[46]; /*0100 01B7*/
|
||||
u_int32_t reply_post_producer_index1; /*01B8 01BB*/
|
||||
u_int32_t reply_post_consumer_index1; /*01BC 01BF*/
|
||||
};
|
||||
|
||||
#define MESG_RW_BUFFER_SIZE (256 * 3)
|
||||
|
||||
typedef struct deliver_completeQ {
|
||||
u_int16_t cmdFlag;
|
||||
u_int16_t cmdSMID;
|
||||
@ -805,6 +895,7 @@ struct MessageUnit_UNION
|
||||
struct HBC_MessageUnit hbcmu;
|
||||
struct HBD_MessageUnit0 hbdmu;
|
||||
struct HBE_MessageUnit hbemu;
|
||||
struct HBF_MessageUnit hbfmu;
|
||||
} muu;
|
||||
};
|
||||
/*
|
||||
@ -1232,6 +1323,7 @@ struct CommandControlBlock {
|
||||
#define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
|
||||
#define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
|
||||
#define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */
|
||||
#define ACB_ADAPTER_TYPE_F 0x00000005 /* hbd L IOP */
|
||||
|
||||
struct AdapterControlBlock {
|
||||
u_int32_t adapter_type; /* adapter A,B..... */
|
||||
@ -1268,6 +1360,9 @@ struct AdapterControlBlock {
|
||||
u_int32_t outbound_int_enable;
|
||||
|
||||
struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */
|
||||
uint32_t *message_wbuffer; //0x000 - COMPORT_IN (to be sent to ROC)
|
||||
uint32_t *message_rbuffer; //0x100 - COMPORT_OUT (to be sent to Host)
|
||||
uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA
|
||||
|
||||
u_int8_t adapter_index;
|
||||
u_int8_t irq;
|
||||
@ -1317,6 +1412,7 @@ struct AdapterControlBlock {
|
||||
pCompletion_Q pCompletionQ;
|
||||
int msix_vectors;
|
||||
int rid[2];
|
||||
unsigned long completeQ_phys;
|
||||
};/* HW_DEVICE_EXTENSION */
|
||||
/* acb_flags */
|
||||
#define ACB_F_SCSISTOPADAPTER 0x0001
|
||||
|
||||
Loading…
Reference in New Issue
Block a user