Very early and very *very* lightly tested support for LIVENGOOD chipset
(followon to WISEMAN). Presumably some flavors are also no multimode copper as well.
This commit is contained in:
mjacob
parent
0630faf57d
commit
fa60c9131a
@ -174,7 +174,12 @@ wx_match(parent, match, aux)
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if (PCI_VENDOR(pa->pa_id) != WX_VENDOR_INTEL) {
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return (0);
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}
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if (PCI_PRODUCT(pa->pa_id) != WX_PRODUCT_82452) {
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switch (PCI_PRODUCT(pa->pa_id)) {
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case WX_PRODUCT_82452:
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case WX_PRODUCT_LIVENGOOD:
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case WX_PRODUCT_82452_SC:
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break;
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default:
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return (0);
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}
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return (1);
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@ -224,7 +229,7 @@ wx_attach(parent, self, aux)
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return;
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}
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printf("%s: interrupting at %s\n", sc->wx_name, intrstr);
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sc->revision =
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sc->wx_idnrev = (PCI_PRODUCT(pa->pa_id) << 16) |
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pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff;
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data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
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@ -510,13 +515,23 @@ static wx_softc_t *wxlist;
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static int
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wx_probe(device_t dev)
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{
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if ((pci_get_vendor(dev) == WX_VENDOR_INTEL) &&
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(pci_get_device(dev) == WX_PRODUCT_82452)) {
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device_set_desc(dev, "Intel GigaBit Ethernet");
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return 0;
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}
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if (pci_get_vendor(dev) != WX_VENDOR_INTEL) {
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return (ENXIO);
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}
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switch (pci_get_device(dev)) {
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case WX_PRODUCT_82452:
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device_set_desc(dev, "Intel GigaBit Ethernet (WISEMAN)");
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break;
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case WX_PRODUCT_LIVENGOOD:
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device_set_desc(dev, "Intel GigaBit Ethernet (LIVENGOOD)");
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case WX_PRODUCT_82452_SC:
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device_set_desc(dev, "Intel GigaBit Ethernet (LIVENGOOD_SC)");
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break;
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default:
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return (ENXIO);
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}
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return (0);
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}
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static int
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wx_attach(device_t dev)
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@ -557,7 +572,13 @@ wx_attach(device_t dev)
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}
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}
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s = splimp();
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/*
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* get revision && id...
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*/
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sc->wx_idnrev = (pci_get_device(dev) << 16) | (pci_get_revid(dev));
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/*
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* Enable bus mastering, make sure that the cache line size is right.
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*/
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@ -570,10 +591,6 @@ wx_attach(device_t dev)
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pci_write_config(dev, PCIR_CACHELNSZ, 0x10, 1);
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}
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/*
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* get revision
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*/
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sc->revision = pci_read_config(dev, PCIR_CLASS, 1);
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/*
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* Map control/status registers.
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@ -772,9 +789,9 @@ wx_attach_common(sc)
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/*
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* First, check for revision support.
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*/
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if (sc->revision < 2) {
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printf("%s: cannot support revision %d chips\n",
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sc->wx_name, sc->revision);
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if (sc->wx_idnrev < WX_WISEMAN_2_0) {
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printf("%s: cannot support ID 0x%x, revision %d chips\n",
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sc->wx_name, sc->wx_idnrev >> 16, sc->wx_idnrev & 0xffff);
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return (ENXIO);
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}
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@ -1265,7 +1282,7 @@ wx_check_link(sc)
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sc->wx_name);
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}
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WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT & ~WXTXCW_ANE);
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if (sc->revision == 2)
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if (sc->wx_idnrev < WX_WISEMAN_2_1)
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sc->wx_dcr &= ~WXDCR_TFCE;
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sc->wx_dcr |= WXDCR_SLU;
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WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
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@ -1587,14 +1604,14 @@ wx_hw_stop(sc)
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wx_softc_t *sc;
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{
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u_int32_t icr;
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if (sc->revision == 2) {
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if (sc->wx_idnrev < WX_WISEMAN_2_1) {
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wx_mwi_whackon(sc);
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}
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WRITE_CSR(sc, WXREG_DCR, WXDCR_RST);
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DELAY(20 * 1000);
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WRITE_CSR(sc, WXREG_IMASK, ~0);
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icr = READ_CSR(sc, WXREG_ICR);
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if (sc->revision == 2) {
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if (sc->wx_idnrev < WX_WISEMAN_2_1) {
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wx_mwi_unwhack(sc);
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}
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WX_DISABLE_INT(sc);
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@ -1620,11 +1637,18 @@ wx_hw_initialize(sc)
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{
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int i;
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if (IS_LIVENGOOD(sc)) {
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if ((READ_CSR(sc, WXREG_DSR) & WXDSR_TBIMODE) == 0) {
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printf("%s: no fibre mode detected\n", sc->wx_name);
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return (-1);
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}
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}
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WRITE_CSR(sc, WXREG_VET, 0);
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for (i = 0; i < (WX_VLAN_TAB_SIZE << 2); i += 4) {
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WRITE_CSR(sc, (WXREG_VFTA + i), 0);
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}
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if (sc->revision == 2) {
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if (sc->wx_idnrev < WX_WISEMAN_2_1) {
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wx_mwi_whackon(sc);
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WRITE_CSR(sc, WXREG_RCTL, WXRCTL_RST);
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DELAY(5 * 1000);
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@ -1649,7 +1673,7 @@ wx_hw_initialize(sc)
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i++;
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}
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if (sc->revision == 2) {
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if (sc->wx_idnrev < WX_WISEMAN_2_1) {
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WRITE_CSR(sc, WXREG_RCTL, 0);
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DELAY(1 * 1000);
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wx_mwi_unwhack(sc);
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@ -1668,6 +1692,14 @@ wx_hw_initialize(sc)
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WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr | WXDCR_LRST);
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DELAY(50 * 1000);
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if (IS_LIVENGOOD(sc)) {
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u_int16_t tew;
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wx_read_eeprom(sc, &tew, WX_EEPROM_CTLR2_OFF, 1);
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tew = (tew & WX_EEPROM_CTLR2_SWDPIO) << WX_EEPROM_EXT_SHIFT;
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WRITE_CSR(sc, WXREG_EXCT, (u_int32_t)tew);
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}
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if (sc->wx_dcr & (WXDCR_RFCE|WXDCR_TFCE)) {
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WRITE_CSR(sc, WXREG_FCAL, FC_FRM_CONST_LO);
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WRITE_CSR(sc, WXREG_FCAH, FC_FRM_CONST_HI);
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@ -1678,7 +1710,8 @@ wx_hw_initialize(sc)
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WRITE_CSR(sc, WXREG_FCT, 0);
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}
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WRITE_CSR(sc, WXREG_FLOW_XTIMER, WX_XTIMER_DFLT);
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if (sc->revision == 2) {
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if (sc->wx_idnrev < WX_WISEMAN_2_1) {
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WRITE_CSR(sc, WXREG_FLOW_RCV_HI, 0);
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WRITE_CSR(sc, WXREG_FLOW_RCV_LO, 0);
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sc->wx_dcr &= ~(WXDCR_RFCE|WXDCR_TFCE);
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@ -1848,7 +1881,11 @@ wx_init(xsc)
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WRITE_CSR(sc, WXREG_TDT, 0);
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WRITE_CSR(sc, WXREG_TQSA_HI, 0);
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WRITE_CSR(sc, WXREG_TQSA_LO, 0);
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WRITE_CSR(sc, WXREG_TIPG, WX_TIPG_DFLT);
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if (IS_WISEMAN(sc)) {
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WRITE_CSR(sc, WXREG_TIPG, WX_WISEMAN_TIPG_DFLT);
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} else {
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WRITE_CSR(sc, WXREG_TIPG, WX_LIVENGOOD_TIPG_DFLT);
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}
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WRITE_CSR(sc, WXREG_TIDV, sc->wx_txint_delay);
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WRITE_CSR(sc, WXREG_TCTL, (WXTCTL_CT(WX_COLLISION_THRESHOLD) |
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WXTCTL_COLD(WX_FDX_COLLISION_DX) | WXTCTL_EN));
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@ -2054,6 +2091,7 @@ wx_ifmedia_sts(ifp, ifmr)
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struct ifnet *ifp;
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struct ifmediareq *ifmr;
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{
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u_int32_t dsr;
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struct wx_softc *sc = SOFTC_IFP(ifp);
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ifmr->ifm_status = IFM_AVALID;
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@ -2062,7 +2100,20 @@ wx_ifmedia_sts(ifp, ifmr)
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if (sc->linkup == 0)
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return;
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ifmr->ifm_status |= IFM_ACTIVE|IFM_1000_SX;
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if (READ_CSR(sc, WXREG_DSR) & WXDSR_FD)
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ifmr->ifm_status |= IFM_ACTIVE;
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dsr = READ_CSR(sc, WXREG_DSR);
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if (IS_LIVENGOOD(sc)) {
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if (dsr & WXDSR_1000BT) {
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ifmr->ifm_status |= IFM_1000_SX;
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} else if (dsr & WXDSR_100BT) {
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ifmr->ifm_status |= IFM_100_FX; /* ?? */
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} else {
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ifmr->ifm_status |= IFM_10_T; /* ?? */
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}
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} else {
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ifmr->ifm_status |= IFM_1000_SX;
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}
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if (dsr & WXDSR_FD) {
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ifmr->ifm_active |= IFM_FDX;
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}
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}
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@ -29,10 +29,21 @@
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#define WX_VENDOR_INTEL 0x8086
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#define WX_PRODUCT_82452 0x1000
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#define WX_PRODUCT_LIVENGOOD 0x1001
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#define WX_PRODUCT_82452_SC 0x1003
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#define WX_MMBA 0x10
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#define MWI 0x10 /* Memory Write Invalidate */
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#define WX_CACHELINE_SIZE 0x20
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/* Join PCI ID and revision into one value */
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#define WX_WISEMAN_0 0x10000000
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#define WX_WISEMAN_2_0 0x10000002
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#define WX_WISEMAN_2_1 0x10000003
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#define WX_LIVENGOOD 0x10010000
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#define IS_WISEMAN(sc) ((sc)->wx_idnrev < WX_LIVENGOOD)
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#define IS_LIVENGOOD(sc) (!IS_WISEMAN(sc))
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/*
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* Information about this chipset gathered from a released Intel Linux driver,
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* which was clearly a port of an NT driver.
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@ -107,6 +118,8 @@ typedef struct {
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#define WXREG_DCR 0x00000000
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#define WXREG_DSR 0x00000008
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#define WXREG_EECDR 0x00000010
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#define WXREG_EXCT 0x00000018
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#define WXREG_MDIC 0x00000020
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#define WXREG_FCAL 0x00000028
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#define WXREG_FCAH 0x0000002C
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#define WXREG_FCT 0x00000030
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@ -165,6 +178,11 @@ typedef struct {
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#define WXDCR_LRST 0x8 /* Link Reset */
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#define WXDCR_SLU 0x40 /* Set Link Up */
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#define WXDCR_ILOS 0x80 /* Invert Loss-of-Signal */
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#define WXDCR_100BT 0x100 /* LIVENGOOD: Set 100BaseT */
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#define WXDCR_1000BT 0x200 /* LIVENGOOD: Set 1000BaseT */
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#define WXDCR_BEM32 0x400 /* LIVENGOOD: Set Big Endian 32 (?) */
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#define WXDCR_FRCSPD 0x800 /* LIVENGOOD: Force Speed (?) */
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#define WXDCR_FRCDPX 0x1000 /* LIVENGOOD: Force Full Duplex */
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/*
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* General purpose I/O pins
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@ -201,6 +219,13 @@ typedef struct {
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#define WXDSR_TXCLK 0x4 /* transmit clock running */
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#define WXDSR_RBCLK 0x8 /* receive clock running */
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#define WXDSR_TXOFF 0x10 /* transmit paused */
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#define WXDSR_TBIMODE 0x20 /* LIVENGOOD: Fibre Mode */
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#define WXDSR_100BT 0x40 /* LIVENGOOD: 100BaseT */
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#define WXDSR_1000BT 0x80 /* LIVENGOOD: 1000BaseT */
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#define WXDSR_ASDV 0x300 /* LIVENGOOD: ?? */
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#define WXDSR_MTXCKOK 0x400 /* LIVENGOOD: ?? */
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#define WXDSR_PCI66 0x800 /* LIVENGOOD: 66 MHz bus */
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#define WXDSR_BUS64 0x1000 /* LIVENGOOD: In 64 bit slot */
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/*
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* EEPROM Register Defines
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@ -236,8 +261,10 @@ typedef struct {
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#define WXISR_LSC 0x4 /* link status change */
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#define WXISR_RXSEQ 0x8 /* receive sequence error */
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#define WXISR_RXDMT0 0x10 /* receiver ring 0 getting empty */
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#define WXISR_RXDMT1 0x20 /* receiver ring 1 getting empty */
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#define WXISR_RXO 0x40 /* receiver overrun */
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#define WXISR_RXT0 0x80 /* ring 0 receiver timer interrupt */
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#define WXISR_RXT1 0x100 /* ring 1 receiver timer interrupt */
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#define WXISR_PCIE 0x200 /* ?? Probably PCI interface error... */
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#define WXIENABLE_DEFAULT \
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@ -256,12 +283,17 @@ typedef struct {
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#define WXRCTL_MPE 0x10 /* multicast promiscuous mode */
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#define WXRCTL_LPE 0x20 /* large packet enable */
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#define WXRCTL_BAM 0x8000 /* broadcast accept mode */
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#define WXRCTL_BSEX 0x2000000 /* LIVENGOOD: Buffer Size Extension */
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#define WXRCTL_2KRBUF (0 << 16) /* 2-Kbyte Receive Buffers */
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#define WXRCTL_1KRBUF (1 << 16) /* 1-Kbyte Receive Buffers */
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#define WXRCTL_2KRBUF (0 << 16) /* 2KB Receive Buffers */
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#define WXRCTL_1KRBUF (1 << 16) /* 1KB Receive Buffers */
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#define WXRCTL_512BRBUF (2 << 16) /* 512 Byte Receive Buffers */
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#define WXRCTL_256BRBUF (3 << 16) /* 256 Byte Receive Buffers */
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#define WXRCTL_4KRBUF (3 << 16) /* LIVENGOOD: 4KB Receive Buffers */
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#define WXRCTL_8KRBUF (2 << 16) /* LIVENGOOD: 8KB Receive Buffers */
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#define WXRCTL_16KRBUF (1 << 16) /* LIVENGOOD: 16KB Receive Buffers */
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/*
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* Receive Delay Timer Register bits.
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@ -327,12 +359,17 @@ typedef struct {
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#define WX_EEPROM_CTLR1_SWDPIO_SHIFT 5
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#define WX_EEPROM_CTLR1_ILOS (1 << 4)
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#define WX_EEPROM_CTLR2_OFF 0xF
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#define WX_EEPROM_CTLR2_SWDPIO 0xF0
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#define WX_EEPROM_EXT_SHIFT 4
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#define WX_XTIMER_DFLT 0x100
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#define WX_RCV_FLOW_HI_DFLT 0x8000
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#define WX_RCV_FLOW_LO_DFLT 0x4000
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#define WX_TIPG_DFLT (10 | (2 << 10) | (10 << 20))
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#define WX_WISEMAN_TIPG_DFLT (10 | (2 << 10) | (10 << 20))
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#define WX_LIVENGOOD_TIPG_DFLT (6 | (8 << 10) | (6 << 20))
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#define WX_CRC_LENGTH 4
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@ -203,6 +203,87 @@ struct wxmdvar {
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#define WRITE_CSR(sc, reg, val) \
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bus_space_write_4((sc)->w.st, (sc)->w.sh, (reg), (val))
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#elif defined(__OpenBSD__)
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/protosw.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/device.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_types.h>
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#include <net/if_media.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/in_systm.h>
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#include <netinet/in_var.h>
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#include <netinet/ip.h>
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#include <netinet/if_ether.h>
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#endif
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#ifdef NS
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#include <netns/ns.h>
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#include <netns/ns_if.h>
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#endif
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#include "bpfilter.h"
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#include <net/bpfdesc.h>
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#endif
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/vm_kern.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/if_wxreg.h>
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struct wxmdvar {
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struct device dev; /* generic device structures */
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void * ih; /* interrupt handler cookie */
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struct arpcom arpcom; /* ethernet common part */
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pci_chipset_tag_t pci_pc;
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pcitag_t pci_tag;
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u_int32_t cmdw;
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bus_space_tag_t st; /* bus space tag */
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bus_space_handle_t sh; /* bus space handle */
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struct ifmedia ifm;
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struct wx_softc * next;
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};
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#define wx_dev w.dev
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#define wx_enaddr w.arpcom.ac_enaddr
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#define wx_cmdw w.cmdw
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#define wx_media w.ifm
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#define wx_next w.next
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#define wx_if w.arpcom.ac_if
|
||||
#define wx_name w.dev.dv_xname
|
||||
|
||||
#define IOCTL_CMD_TYPE u_long
|
||||
#define WXMALLOC(len) malloc(len, M_DEVBUF, M_NOWAIT)
|
||||
#define WXFREE(ptr) free(ptr, M_DEVBUF)
|
||||
#define SOFTC_IFP(ifp) ifp->if_softc
|
||||
#define WX_BPFTAP_ARG(ifp) (ifp)->if_bpf
|
||||
#define TIMEOUT(sc, func, arg, time) timeout(func, arg, time)
|
||||
#define VTIMEOUT(sc, func, arg, time) timeout(func, arg, time)
|
||||
#define UNTIMEOUT(f, arg, sc) untimeout(f, arg)
|
||||
#define INLINE inline
|
||||
|
||||
#define vm_offset_t vaddr_t
|
||||
#define READ_CSR _read_csr
|
||||
#define WRITE_CSR _write_csr
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@ -235,16 +316,15 @@ typedef struct wx_softc {
|
||||
/*
|
||||
* misc goodies
|
||||
*/
|
||||
u_int32_t : 17,
|
||||
u_int32_t : 25,
|
||||
wx_no_flow : 1,
|
||||
wx_ilos : 1,
|
||||
wx_no_ilos : 1,
|
||||
wx_debug : 1,
|
||||
ane_failed : 1,
|
||||
linkup : 1,
|
||||
all_mcasts : 1,
|
||||
revision : 8; /* chip revision */
|
||||
|
||||
all_mcasts : 1;
|
||||
u_int32_t wx_idnrev; /* chip revision && PCI ID */
|
||||
u_int16_t wx_cfg1;
|
||||
u_int16_t wx_txint_delay;
|
||||
u_int32_t wx_ienable; /* current ienable to use */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user