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The IPMI spec is ambiguous (or rather, it contradicts itself) about whether

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or not the OS has to wait for RX_RDY or TX_RDY to be set before the OS sets
the control code in the control/status register.  Looking at the interface
design, it seems that RX_RDY and TX_RDY are probably there to protect
access to the data register and have nothing to do with the control/status
register.  Nevertheless, try to take what I think is the more conservative
approach and always wait for the appropriate [TR]X_RDY flag to be set
before writing any of the WR_NEXT, WR_END, RD_START, or RD_NEXT control
codes to the control/status register.
This commit is contained in:
John Baldwin 2006-10-05 15:38:59 +00:00
parent b4828cc1dd
commit fab2d1adf6
1 changed files with 4 additions and 4 deletions
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8
sys/dev/ipmi/ipmi_smic.c
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@ -127,8 +127,8 @@ smic_write_next(struct ipmi_softc *sc, u_char data)
{
u_char error, status;
OUTB(sc, SMIC_CTL_STS, SMIC_CC_SMS_WR_NEXT);
smic_wait_for_tx_okay(sc);
OUTB(sc, SMIC_CTL_STS, SMIC_CC_SMS_WR_NEXT);
OUTB(sc, SMIC_DATA, data);
smic_set_busy(sc);
smic_wait_for_not_busy(sc);
@ -151,8 +151,8 @@ smic_write_last(struct ipmi_softc *sc, u_char data)
{
u_char error, status;
OUTB(sc, SMIC_CTL_STS, SMIC_CC_SMS_WR_END);
smic_wait_for_tx_okay(sc);
OUTB(sc, SMIC_CTL_STS, SMIC_CC_SMS_WR_END);
OUTB(sc, SMIC_DATA, data);
smic_set_busy(sc);
smic_wait_for_not_busy(sc);
@ -176,8 +176,8 @@ smic_start_read(struct ipmi_softc *sc, u_char *data)
smic_wait_for_not_busy(sc);
OUTB(sc, SMIC_CTL_STS, SMIC_CC_SMS_RD_START);
smic_wait_for_rx_okay(sc);
OUTB(sc, SMIC_CTL_STS, SMIC_CC_SMS_RD_START);
smic_set_busy(sc);
smic_wait_for_not_busy(sc);
status = INB(sc, SMIC_CTL_STS);
@ -200,8 +200,8 @@ smic_read_byte(struct ipmi_softc *sc, u_char *data)
{
u_char error, status;
OUTB(sc, SMIC_CTL_STS, SMIC_SC_SMS_RD_NEXT);
smic_wait_for_rx_okay(sc);
OUTB(sc, SMIC_CTL_STS, SMIC_SC_SMS_RD_NEXT);
smic_set_busy(sc);
smic_wait_for_not_busy(sc);
status = INB(sc, SMIC_CTL_STS);