Add a driver for the Intersil ISL12xx family of i2c RTC chips.
Supports ISL1209, ISL1218, ISL1219, ISL1220, ISL1221 (just basic RTC functionality, not all the other fancy stuff the chips can do).
This commit is contained in:
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@ -1736,6 +1736,7 @@ dev/iicbus/iiconf.c optional iicbus
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dev/iicbus/iicsmb.c optional iicsmb \
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dependency "iicbus_if.h"
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dev/iicbus/iicoc.c optional iicoc
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dev/iicbus/isl12xx.c optional isl12xx
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dev/iicbus/lm75.c optional lm75
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dev/iicbus/nxprtc.c optional nxprtc | pcf8563
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dev/iicbus/ofw_iicbus.c optional fdt iicbus
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354
sys/dev/iicbus/isl12xx.c
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354
sys/dev/iicbus/isl12xx.c
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@ -0,0 +1,354 @@
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/*-
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* Copyright (c) 2017 Ian Lepore. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Driver for ISL12xx family i2c realtime clocks:
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* - ISL1209 = 2B sram, tamper/event timestamp
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* - ISL1218 = 8B sram, DS13xx pin compatible (but not software compatible)
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* - ISL1219 = 2B sram, tamper/event timestamp
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* - ISL1220 = 8B sram, separate Fout
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* - ISL1221 = 2B sram, separate Fout, tamper/event timestamp
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*
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* This driver supports only the basic RTC functionality in all these chips.
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*/
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/clock.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/sx.h>
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#ifdef FDT
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#endif
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include "clock_if.h"
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#include "iicbus_if.h"
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/*
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* All register and bit names as found in the datasheet. When a bit name ends
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* in 'B' that stands for "bar" and it is an active-low signal; something named
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* "EVENB" implies 1=event-disable, 0=event-enable.
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*/
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#define ISL12XX_SC_REG 0x00 /* RTC Seconds */
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#define ISL12XX_SR_REG 0x07 /* Status */
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#define ISL12XX_SR_ARST (1u << 7) /* Auto-reset on status read */
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#define ISL12XX_SR_XTOSCB (1u << 5) /* Osc disable (use ext osc) */
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#define ISL12XX_SR_WRTC (1u << 4) /* Write RTC enable */
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#define ISL12XX_SR_EVT (1u << 3) /* Event occurred (w0c) */
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#define ISL12XX_SR_ALM (1u << 2) /* Alarm occurred (w0c) */
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#define ISL12XX_SR_BAT (1u << 1) /* Running on battery (w0c) */
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#define ISL12XX_SR_RTCF (1u << 0) /* RTC fail (power loss) */
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#define ISL12XX_SR_W0C_BITS (ISL12XX_SR_BAT | ISL12XX_SR_ALM | ISL12XX_SR_EVT)
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#define ISL12XX_INT_REG 0x08 /* Interrupts */
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#define ISL12XX_INT_IM (1u << 7) /* Alarm interrupt mode */
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#define ISL12XX_INT_ALME (1u << 6) /* Alarm enable */
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#define ISL12XX_INT_LPMODE (1u << 5) /* Low Power mode */
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#define ISL12XX_INT_FOBATB (1u << 4) /* Fout/IRQ disabled on bat */
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#define ISL12XX_INT_FO_SHIFT 0 /* Frequency output select */
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#define ISL12XX_INT_FO_MASK 0x0f /* shift and mask. */
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#define ISL12XX_EV_REG 0x09 /* Event */
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#define ISL12XX_EV_EVIENB (1u << 7) /* Disable internal pullup */
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#define ISL12XX_EV_EVBATB (1u << 6) /* Disable ev detect on bat */
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#define ISL12XX_EV_RTCHLT (1u << 5) /* Halt RTC on event */
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#define ISL12XX_EV_EVEN (1u << 4) /* Event detect enable */
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#define ISL12XX_EV_EHYS_SHIFT 2 /* Event input hysteresis */
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#define ISL12XX_EV_EHYS_MASK 0x03 /* selection; see datasheet */
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#define ISL12XX_EV_ESMP_SHIFT 0 /* Event input sample rate */
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#define ISL12XX_EV_ESMP_MASK 0x03 /* selection; see datasheet */
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#define ISL12XX_ATR_REG 0x0a /* Analog trim (osc adjust) */
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#define ISL12XX_DTR_REG 0x0b /* Digital trim (osc adjust) */
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#define ISL12XX_SCA_REG 0x0c /* Alarm seconds */
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#define ISL12XX_USR1_REG 0x12 /* User byte 1 */
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#define ISL12XX_USR2_REG 0x13 /* User byte 2 */
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#define ISL12XX_SCT_REG 0x14 /* Timestamp (event) seconds */
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#define ISL12XX_24HR_FLAG (1u << 7) /* Hours register 24-hr mode */
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#define ISL12XX_PM_FLAG (1u << 5) /* Hours register PM flag */
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#define ISL12xx_12HR_MASK 0x1f /* Hours mask in AM/PM mode */
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#define ISL12xx_24HR_MASK 0x3f /* Hours mask in 24-hr mode */
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/*
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* A struct laid out in the same order as the time registers in the chip.
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*/
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struct time_regs {
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uint8_t sec, min, hour, day, month, year;
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};
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struct isl12xx_softc {
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device_t dev;
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device_t busdev;
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struct intr_config_hook
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init_hook;
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bool use_ampm;
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};
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#ifdef FDT
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static struct ofw_compat_data compat_data[] = {
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{"isil,isl1209", 1},
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{"isil,isl1218", 1},
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{"isil,isl1219", 1},
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{"isil,isl1220", 1},
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{"isil,isl1221", 1},
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{NULL, 0},
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};
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#endif
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static inline int
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isl12xx_read1(struct isl12xx_softc *sc, uint8_t reg, uint8_t *data)
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{
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return (iicdev_readfrom(sc->dev, reg, data, 1, IIC_WAIT));
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}
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static inline int
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isl12xx_write1(struct isl12xx_softc *sc, uint8_t reg, uint8_t val)
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{
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return (iicdev_writeto(sc->dev, reg, &val, 1, IIC_WAIT));
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}
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static void
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isl12xx_init(void *arg)
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{
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struct isl12xx_softc *sc = arg;
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uint8_t sreg;
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config_intrhook_disestablish(&sc->init_hook);
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/*
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* Check the clock-stopped/power-fail bit, just so we can report it to
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* the user at boot time.
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*/
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isl12xx_read1(sc, ISL12XX_SR_REG, &sreg);
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if (sreg & ISL12XX_SR_RTCF) {
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device_printf(sc->dev,
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"RTC clock stopped; check battery\n");
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}
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/*
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* Register as a system realtime clock.
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*/
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clock_register_flags(sc->dev, 1000000, CLOCKF_SETTIME_NO_ADJ);
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clock_schedule(sc->dev, 1);
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}
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static int
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isl12xx_probe(device_t dev)
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{
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#ifdef FDT
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
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device_set_desc(dev, "Intersil ISL12xx RTC");
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return (BUS_PROBE_DEFAULT);
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}
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#endif
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return (ENXIO);
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}
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static int
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isl12xx_attach(device_t dev)
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{
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struct isl12xx_softc *sc = device_get_softc(dev);
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sc->dev = dev;
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sc->busdev = device_get_parent(sc->dev);
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/*
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* Chip init must wait until interrupts are enabled. Often i2c access
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* works only when the interrupts are available.
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*/
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sc->init_hook.ich_func = isl12xx_init;
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sc->init_hook.ich_arg = sc;
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if (config_intrhook_establish(&sc->init_hook) != 0)
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return (ENOMEM);
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return (0);
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}
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static int
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isl12xx_detach(device_t dev)
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{
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clock_unregister(dev);
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return (0);
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}
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static int
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isl12xx_gettime(device_t dev, struct timespec *ts)
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{
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struct isl12xx_softc *sc = device_get_softc(dev);
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struct clocktime ct;
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struct time_regs tregs;
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int err;
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uint8_t hourmask, sreg;
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/* If power failed, we can't provide valid time. */
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if ((err = isl12xx_read1(sc, ISL12XX_SR_REG, &sreg)) != 0)
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return (err);
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if (sreg & ISL12XX_SR_RTCF)
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return (EINVAL);
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/* Read the bcd time registers. */
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if ((err = iicdev_readfrom(sc->dev, ISL12XX_SC_REG, &tregs, sizeof(tregs),
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IIC_WAIT)) != 0)
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return (EINVAL);
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/* If chip is in AM/PM mode remember that for when we set time. */
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if (tregs.hour & ISL12XX_24HR_FLAG) {
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hourmask = ISL12xx_24HR_MASK;
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} else {
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sc->use_ampm = true;
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hourmask = ISL12xx_12HR_MASK;
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}
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ct.nsec = 0;
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ct.sec = FROMBCD(tregs.sec);
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ct.min = FROMBCD(tregs.min);
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ct.hour = FROMBCD(tregs.hour & hourmask);
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ct.day = FROMBCD(tregs.day);
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ct.mon = FROMBCD(tregs.month);
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ct.year = FROMBCD(tregs.year);
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if (sc->use_ampm) {
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if (ct.hour == 12)
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ct.hour = 0;
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if (tregs.hour & ISL12XX_PM_FLAG)
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ct.hour += 12;
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}
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return (clock_ct_to_ts(&ct, ts));
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}
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static int
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isl12xx_settime(device_t dev, struct timespec *ts)
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{
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struct isl12xx_softc *sc = device_get_softc(dev);
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struct clocktime ct;
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struct time_regs tregs;
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int err;
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uint8_t ampmflags, sreg;
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/*
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* We request a timespec with no resolution-adjustment. That also
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* disables utc adjustment, so apply that ourselves.
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*/
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ts->tv_sec -= utc_offset();
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ts->tv_nsec = 0;
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clock_ts_to_ct(ts, &ct);
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/* If the chip is in AM/PM mode, adjust hour and set flags as needed. */
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if (!sc->use_ampm) {
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ampmflags = ISL12XX_24HR_FLAG;
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} else {
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ampmflags = 0;
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if (ct.hour >= 12) {
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ct.hour -= 12;
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ampmflags |= ISL12XX_PM_FLAG;
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}
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if (ct.hour == 0)
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ct.hour = 12;
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}
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tregs.sec = TOBCD(ct.sec);
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tregs.min = TOBCD(ct.min);
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tregs.hour = TOBCD(ct.hour) | ampmflags;
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tregs.day = TOBCD(ct.day);
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tregs.month = TOBCD(ct.mon);
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tregs.year = TOBCD(ct.year % 100);
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/*
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* To set the time we have to set the WRTC enable bit in the control
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* register, then write the time regs, then clear the WRTC bit. While
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* doing so we have to be careful to not write a 0 to any sreg bit which
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* is "write 0 to clear". One of those bits could get set between
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* reading and writing the register. All those bits ignore attempts to
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* write a 1, so just always OR-in all the W0C bits to be sure we never
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* accidentally clear one. We hold ownership of the i2c bus for the
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* whole read-modify-write sequence.
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*/
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if ((err = iicbus_request_bus(sc->busdev, sc->dev, IIC_WAIT)) != 0)
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return (err);
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if ((err = isl12xx_read1(sc, ISL12XX_SR_REG, &sreg)) == 0) {
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sreg |= ISL12XX_SR_WRTC | ISL12XX_SR_W0C_BITS;
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if ((err = isl12xx_write1(sc, ISL12XX_SR_REG, sreg)) == 0) {
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err = iicdev_writeto(sc->dev, ISL12XX_SC_REG, &tregs,
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sizeof(tregs), IIC_WAIT);
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sreg &= ~ISL12XX_SR_WRTC;
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isl12xx_write1(sc, ISL12XX_SR_REG, sreg);
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}
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}
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iicbus_release_bus(sc->busdev, sc->dev);
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return (err);
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}
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static device_method_t isl12xx_methods[] = {
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/* device_if methods */
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DEVMETHOD(device_probe, isl12xx_probe),
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DEVMETHOD(device_attach, isl12xx_attach),
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DEVMETHOD(device_detach, isl12xx_detach),
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/* clock_if methods */
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DEVMETHOD(clock_gettime, isl12xx_gettime),
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DEVMETHOD(clock_settime, isl12xx_settime),
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DEVMETHOD_END,
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};
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static driver_t isl12xx_driver = {
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"isl12xx",
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isl12xx_methods,
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sizeof(struct isl12xx_softc),
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};
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static devclass_t isl12xx_devclass;
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DRIVER_MODULE(isl12xx, iicbus, isl12xx_driver, isl12xx_devclass, NULL, NULL);
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MODULE_VERSION(isl12xx, 1);
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MODULE_DEPEND(isl12xx, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
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@ -11,6 +11,7 @@ SUBDIR = \
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iicbus \
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iicsmb \
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isl \
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isl12xx \
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jedec_ts \
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nxprtc \
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smb \
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7
sys/modules/i2c/isl12xx/Makefile
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7
sys/modules/i2c/isl12xx/Makefile
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@ -0,0 +1,7 @@
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# $FreeBSD$
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.PATH: ${SRCTOP}/sys/dev/iicbus
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KMOD = isl12xx
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SRCS = isl12xx.c bus_if.h clock_if.h device_if.h iicbus_if.h
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.include <bsd.kmod.mk>
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