Add RISC-V ELF machine type definition

EM_RISCV is now officially registered as e_machine 243.

MFC after:	1 month
Sponsored by:	The FreeBSD Foundation
This commit is contained in:
emaste 2015-07-24 16:52:21 +00:00
parent 9c81c0faa6
commit faf3fc6a75
4 changed files with 5 additions and 1 deletions

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@ -813,7 +813,8 @@ _ELF_DEFINE_EM(EM_KM32, 210, "KM211 KM32 32-bit processor") \
_ELF_DEFINE_EM(EM_KMX32, 211, "KM211 KMX32 32-bit processor") \
_ELF_DEFINE_EM(EM_KMX16, 212, "KM211 KMX16 16-bit processor") \
_ELF_DEFINE_EM(EM_KMX8, 213, "KM211 KMX8 8-bit processor") \
_ELF_DEFINE_EM(EM_KVARC, 214, "KM211 KMX32 KVARC processor")
_ELF_DEFINE_EM(EM_KVARC, 214, "KM211 KMX32 KVARC processor") \
_ELF_DEFINE_EM(EM_RISCV, 243, "RISC-V")
#undef _ELF_DEFINE_EM
#define _ELF_DEFINE_EM(N, V, DESCR) N = V ,

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@ -532,6 +532,7 @@ elf_machine(unsigned int mach)
case EM_ARCA: return "Arca RISC Microprocessor";
case EM_UNICORE: return "Microprocessor series from PKU-Unity Ltd";
case EM_AARCH64: return "AArch64";
case EM_RISCV: return "RISC-V";
default:
snprintf(s_mach, sizeof(s_mach), "<unknown: %#x>", mach);
return (s_mach);

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@ -297,6 +297,7 @@ typedef struct {
#define EM_UNICORE 110 /* Microprocessor series from PKU-Unity Ltd.
and MPRC of Peking University */
#define EM_AARCH64 183 /* AArch64 (64-bit ARM) */
#define EM_RISCV 243 /* RISC-V */
/* Non-standard or deprecated. */
#define EM_486 6 /* Intel i486. */

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@ -272,6 +272,7 @@ e_machines(u_int mach)
case EM_IA_64: return "EM_IA_64";
case EM_X86_64: return "EM_X86_64";
case EM_AARCH64:return "EM_AARCH64";
case EM_RISCV: return "EM_RISCV";
}
snprintf(machdesc, sizeof(machdesc),
"(unknown machine) -- type 0x%x", mach);