a10_ahci: Correct clock indices for new bindings
r329104 imported 4.15 DTS which brought CCU to a10/a20. In the process, they swapped the ordering of 'clocks' for allwinner,sun4i-a10-ahci on both sun4i-a10 and sun7i-a20 from PLL, Gate to Gate, PLL. Swap it in the driver.
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@ -313,16 +313,16 @@ ahci_a10_attach(device_t dev)
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return (ENXIO);
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/* Enable clocks */
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error = clk_get_by_ofw_index(dev, 0, 0, &clk_pll);
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if (error != 0) {
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device_printf(dev, "Cannot get PLL clock\n");
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goto fail;
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}
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error = clk_get_by_ofw_index(dev, 0, 1, &clk_gate);
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error = clk_get_by_ofw_index(dev, 0, 0, &clk_gate);
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if (error != 0) {
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device_printf(dev, "Cannot get gate clock\n");
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goto fail;
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}
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error = clk_get_by_ofw_index(dev, 0, 1, &clk_pll);
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if (error != 0) {
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device_printf(dev, "Cannot get PLL clock\n");
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goto fail;
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}
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error = clk_set_freq(clk_pll, PLL_FREQ, CLK_SET_ROUND_DOWN);
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if (error != 0) {
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device_printf(dev, "Cannot set PLL frequency\n");
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