Allwinner Gigabit EMAC performance improvements.
- Support DEVICE_POLLING - Increase TX descriptors to 1024 - Add support for passing a chain of mbufs to if_input, reducing the number of calls to mtx_unlock/mtx_lock under load. - Remove duplicate byteswap when setting TX_INT_CTL in TX descriptor. - Set undocumented "TX_NEXT_FRAME" bit in TX control 1 register. According to the A83T BSP, setting this bit allows the DMA engine to operate on a packet while receiving another. Tested on A83T (1000Mbps PHY) and H3 (100Mbps PHY). Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D7031
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jmcneill
parent
45e538b37f
commit
fb6c2d6ae3
@ -30,6 +30,8 @@
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* Allwinner Gigabit Ethernet MAC (EMAC) controller
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*/
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#include "opt_device_polling.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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@ -77,7 +79,7 @@ __FBSDID("$FreeBSD$");
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#define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
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#define DESC_ALIGN 4
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#define TX_DESC_COUNT 256
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#define TX_DESC_COUNT 1024
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#define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT)
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#define RX_DESC_COUNT 256
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#define RX_DESC_SIZE (sizeof(struct emac_desc) * RX_DESC_COUNT)
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@ -97,6 +99,7 @@ __FBSDID("$FreeBSD$");
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#define RX_TX_PRI_DEFAULT 0
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#define PAUSE_TIME_DEFAULT 0x400
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#define TX_INTERVAL_DEFAULT 64
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#define RX_BATCH_DEFAULT 64
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/* Burst length of RX and TX DMA transfers */
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static int awg_burst_len = BURST_LEN_DEFAULT;
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@ -114,6 +117,10 @@ TUNABLE_INT("hw.awg.pause_time", &awg_pause_time);
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static int awg_tx_interval = TX_INTERVAL_DEFAULT;
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TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval);
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/* Maximum number of mbufs to send to if_input */
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static int awg_rx_batch = RX_BATCH_DEFAULT;
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TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch);
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun8i-a83t-emac", 1 },
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{ NULL, 0 }
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@ -353,7 +360,7 @@ awg_setup_txdesc(struct awg_softc *sc, int index, int flags, bus_addr_t paddr,
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status = TX_DESC_CTL;
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size = flags | len;
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if ((index & (awg_tx_interval - 1)) == 0)
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size |= htole32(TX_INT_CTL);
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size |= TX_INT_CTL;
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++sc->tx.queued;
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}
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@ -616,6 +623,20 @@ awg_setup_rxfilter(struct awg_softc *sc)
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WR4(sc, EMAC_RX_FRM_FLT, val);
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}
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static void
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awg_enable_intr(struct awg_softc *sc)
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{
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/* Enable interrupts */
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WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN);
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}
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static void
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awg_disable_intr(struct awg_softc *sc)
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{
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/* Disable interrupts */
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WR4(sc, EMAC_INT_EN, 0);
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}
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static void
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awg_init_locked(struct awg_softc *sc)
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{
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@ -640,11 +661,18 @@ awg_init_locked(struct awg_softc *sc)
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WR4(sc, EMAC_BASIC_CTL_1, val);
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/* Enable interrupts */
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WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN);
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#ifdef DEVICE_POLLING
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if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0)
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awg_enable_intr(sc);
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else
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awg_disable_intr(sc);
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#else
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awg_enable_intr(sc);
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#endif
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/* Enable transmit DMA */
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val = RD4(sc, EMAC_TX_CTL_1);
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WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD);
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WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME);
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/* Enable receive DMA */
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val = RD4(sc, EMAC_RX_CTL_1);
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@ -703,7 +731,7 @@ awg_stop(struct awg_softc *sc)
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WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN);
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/* Disable interrupts */
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WR4(sc, EMAC_INT_EN, 0);
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awg_disable_intr(sc);
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/* Disable transmit DMA */
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val = RD4(sc, EMAC_TX_CTL_1);
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@ -718,15 +746,18 @@ awg_stop(struct awg_softc *sc)
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if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
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}
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static void
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static int
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awg_rxintr(struct awg_softc *sc)
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{
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if_t ifp;
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struct mbuf *m, *m0;
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int error, index, len;
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struct mbuf *m, *m0, *mh, *mt;
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int error, index, len, cnt, npkt;
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uint32_t status;
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ifp = sc->ifp;
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mh = mt = NULL;
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cnt = 0;
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npkt = 0;
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bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
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BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
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@ -760,9 +791,23 @@ awg_rxintr(struct awg_softc *sc)
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}
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}
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AWG_UNLOCK(sc);
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if_input(ifp, m);
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AWG_LOCK(sc);
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m->m_nextpkt = NULL;
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if (mh == NULL)
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mh = m;
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else
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mt->m_nextpkt = m;
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mt = m;
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++cnt;
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++npkt;
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if (cnt == awg_rx_batch) {
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AWG_UNLOCK(sc);
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if_input(ifp, mh);
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AWG_LOCK(sc);
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mh = mt = NULL;
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cnt = 0;
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}
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}
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if ((m0 = awg_alloc_mbufcl(sc)) != NULL) {
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@ -779,7 +824,15 @@ awg_rxintr(struct awg_softc *sc)
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BUS_DMASYNC_PREWRITE);
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}
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if (mh != NULL) {
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AWG_UNLOCK(sc);
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if_input(ifp, mh);
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AWG_LOCK(sc);
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}
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sc->rx.cur = index;
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return (npkt);
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}
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static void
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@ -845,6 +898,41 @@ awg_intr(void *arg)
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AWG_UNLOCK(sc);
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}
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#ifdef DEVICE_POLLING
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static int
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awg_poll(if_t ifp, enum poll_cmd cmd, int count)
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{
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struct awg_softc *sc;
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uint32_t val;
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int rx_npkts;
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sc = if_getsoftc(ifp);
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rx_npkts = 0;
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AWG_LOCK(sc);
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if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
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AWG_UNLOCK(sc);
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return (0);
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}
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rx_npkts = awg_rxintr(sc);
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awg_txintr(sc);
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if (!if_sendq_empty(ifp))
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awg_start_locked(sc);
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if (cmd == POLL_AND_CHECK_STATUS) {
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val = RD4(sc, EMAC_INT_STA);
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if (val != 0)
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WR4(sc, EMAC_INT_STA, val);
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}
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AWG_UNLOCK(sc);
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return (rx_npkts);
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}
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#endif
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static int
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awg_ioctl(if_t ifp, u_long cmd, caddr_t data)
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{
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@ -889,6 +977,25 @@ awg_ioctl(if_t ifp, u_long cmd, caddr_t data)
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break;
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case SIOCSIFCAP:
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mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
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#ifdef DEVICE_POLLING
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if (mask & IFCAP_POLLING) {
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if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
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error = ether_poll_register(awg_poll, ifp);
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if (error != 0)
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break;
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AWG_LOCK(sc);
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awg_disable_intr(sc);
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if_setcapenablebit(ifp, IFCAP_POLLING, 0);
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AWG_UNLOCK(sc);
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} else {
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error = ether_poll_deregister(ifp);
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AWG_LOCK(sc);
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awg_enable_intr(sc);
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if_setcapenablebit(ifp, 0, IFCAP_POLLING);
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AWG_UNLOCK(sc);
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}
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}
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#endif
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if (mask & IFCAP_VLAN_MTU)
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if_togglecapenable(ifp, IFCAP_VLAN_MTU);
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if (mask & IFCAP_RXCSUM)
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@ -1374,6 +1481,9 @@ awg_attach(device_t dev)
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if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP);
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if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM);
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if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp));
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#ifdef DEVICE_POLLING
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if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0);
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#endif
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/* Attach MII driver */
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error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change,
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@ -65,6 +65,7 @@
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#define EMAC_TX_CTL_1 0x14
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#define TX_DMA_START (1 << 31)
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#define TX_DMA_EN (1 << 30)
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#define TX_NEXT_FRAME (1 << 2)
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#define TX_MD (1 << 1)
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#define FLUSH_TX_FIFO (1 << 0)
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#define EMAC_TX_FLOW_CTL 0x1c
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