Add some incomplete support for Marvell Yukon EC controllers based on
OpenBSD changes. With these changes, PHY part of the driver becomes functional (it senses media changes and negotiates speed just fine), previously it just hang with no PHY message, but no data goes through interface (error message is "can not stop transfer of Tx/Rx descriptor). Hopefully somebody with more clue/free time will be able to pick up after me.
This commit is contained in:
sobomax
parent
eee673a6a7
commit
fc40fabe0b
@ -159,6 +159,21 @@ static struct sk_type sk_devs[] = {
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DEVICEID_SK_V2,
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"Marvell Gigabit Ethernet"
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},
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{
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VENDORID_MARVELL,
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DEVICEID_MRVL_4360,
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"Marvell 88E8052 Gigabit Ethernet Controller"
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},
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{
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VENDORID_MARVELL,
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DEVICEID_MRVL_4361,
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"Marvell 88E8050 Gigabit Ethernet Controller"
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},
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{
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VENDORID_MARVELL,
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DEVICEID_MRVL_4362,
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"Marvell 88E8053 Gigabit Ethernet Controller"
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},
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{
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VENDORID_MARVELL,
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DEVICEID_BELKIN_5005,
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@ -571,6 +586,7 @@ sk_miibus_readreg(dev, phy, reg)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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v = sk_marv_miibus_readreg(sc_if, phy, reg);
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break;
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default:
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@ -600,6 +616,7 @@ sk_miibus_writereg(dev, phy, reg, val)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
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break;
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default:
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@ -627,6 +644,7 @@ sk_miibus_statchg(dev)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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sk_marv_miibus_statchg(sc_if);
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break;
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}
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@ -852,6 +870,7 @@ sk_setmulti(sc_if)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
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SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
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SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
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@ -893,6 +912,7 @@ sk_setmulti(sc_if)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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bcopy(LLADDR(
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(struct sockaddr_dl *)ifma->ifma_addr),
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maddr, ETHER_ADDR_LEN);
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@ -917,6 +937,7 @@ sk_setmulti(sc_if)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
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SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
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SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
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@ -947,6 +968,7 @@ sk_setpromisc(sc_if)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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if (ifp->if_flags & IFF_PROMISC) {
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SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
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YU_RCR_UFLEN | YU_RCR_MUFLEN);
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@ -1395,6 +1417,9 @@ sk_reset(sc)
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case SK_GENESIS:
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sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
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break;
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case SK_YUKON_EC:
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sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON_EC;
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break;
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default:
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sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
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break;
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@ -1432,6 +1457,7 @@ sk_probe(dev)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
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break;
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}
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@ -1527,8 +1553,12 @@ sk_attach(dev)
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* receiver and b) between the two XMACs, if this is a
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* dual port NIC. Our algotithm is to divide up the memory
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* evenly so that everyone gets a fair share.
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*
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* Just to be contrary, Yukon2 appears to have separate memory
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* for each MAC.
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*/
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if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
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if (SK_IS_YUKON2(sc) ||
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sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
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u_int32_t chunk, val;
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chunk = sc->sk_ramsize / 2;
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@ -1555,22 +1585,32 @@ sk_attach(dev)
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/* Read and save PHY type and set PHY address */
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sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
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switch(sc_if->sk_phytype) {
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case SK_PHYTYPE_XMAC:
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sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
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break;
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case SK_PHYTYPE_BCOM:
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sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
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break;
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case SK_PHYTYPE_MARV_COPPER:
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if (!SK_YUKON_FAMILY(sc->sk_type)) {
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switch(sc_if->sk_phytype) {
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case SK_PHYTYPE_XMAC:
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sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
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break;
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case SK_PHYTYPE_BCOM:
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sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
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break;
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default:
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device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
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sc_if->sk_phytype);
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error = ENODEV;
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SK_IF_UNLOCK(sc_if);
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goto fail;
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}
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} else {
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if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
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sc->sk_pmd == IFM_1000_T) {
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/* not initialized, punt */
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sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
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}
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sc_if->sk_phyaddr = SK_PHYADDR_MARV;
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break;
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default:
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device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
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sc_if->sk_phytype);
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error = ENODEV;
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SK_IF_UNLOCK(sc_if);
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goto fail;
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if (sc->sk_pmd != IFM_1000_T && sc->sk_pmd != IFM_1000_CX)
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sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
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}
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/*
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@ -1605,6 +1645,7 @@ sk_attach(dev)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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sk_init_yukon(sc_if);
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break;
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}
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@ -1637,7 +1678,7 @@ skc_attach(dev)
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device_t dev;
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{
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struct sk_softc *sc;
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int error = 0, rid, *port;
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int error = 0, rid, *port, sk_macs;
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uint8_t skrs;
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char *pname, *revstr;
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@ -1759,6 +1800,12 @@ skc_attach(dev)
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sc->sk_pmd = IFM_1000_T;
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break;
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default:
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if (SK_YUKON_FAMILY(sc->sk_type) && (sk_win_read_1(sc, SK_EPROM1)
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& 0xF) < SK_PHYTYPE_MARV_COPPER) {
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/* not initialized, punt */
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sc->sk_pmd = IFM_1000_T;
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break;
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}
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device_printf(dev, "unknown media type: 0x%x\n",
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sk_win_read_1(sc, SK_PMDTYPE));
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error = ENXIO;
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@ -1777,6 +1824,9 @@ skc_attach(dev)
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pname = sc->sk_vpd_prodname;
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break;
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case DEVICEID_SK_V2:
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case DEVICEID_MRVL_4360:
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case DEVICEID_MRVL_4361:
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case DEVICEID_MRVL_4362:
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/* YUKON VPD PN might bear no resemblance to reality. */
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switch (sc->sk_type) {
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case SK_GENESIS:
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@ -1792,6 +1842,9 @@ skc_attach(dev)
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case SK_YUKON_LP:
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pname = "Marvell Yukon LP Gigabit Ethernet";
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break;
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case SK_YUKON_EC:
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pname = "Marvell Yukon-2 EC Gigabit Ethernet";
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break;
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default:
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pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
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break;
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@ -1841,6 +1894,21 @@ skc_attach(dev)
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revstr = "";
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break;
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}
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} else if (sc->sk_type == SK_YUKON_EC) {
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switch (sc->sk_rev) {
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case SK_YUKON_EC_REV_A1:
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revstr = "A1";
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break;
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case SK_YUKON_EC_REV_A2:
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revstr = "A2";
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break;
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case SK_YUKON_EC_REV_A3:
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revstr = "A3";
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break;
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default:
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revstr = "";
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break;
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}
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} else {
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revstr = "";
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}
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@ -1899,7 +1967,23 @@ skc_attach(dev)
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*port = SK_PORT_A;
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device_set_ivars(sc->sk_devs[SK_PORT_A], port);
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if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
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sk_macs = 1;
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if (SK_IS_YUKON2(sc)) {
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u_int8_t hw;
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hw = sk_win_read_1(sc, SK_Y2_HWRES);
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if ((hw & SK_Y2_HWRES_LINK_MASK) == SK_Y2_HWRES_LINK_DUAL) {
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if ((sk_win_read_1(sc, SK_Y2_CLKGATE) &
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SK_Y2_CLKGATE_LINK2_INACTIVE) == 0)
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sk_macs++;
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}
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} else {
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if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC))
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sk_macs++;
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}
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if (sk_macs > 1) {
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sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
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if (sc->sk_devs[SK_PORT_B] == NULL) {
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device_printf(dev, "failed to add child for PORT_B\n");
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@ -3813,6 +3897,7 @@ sk_init_locked(sc_if)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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sk_init_yukon(sc_if);
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break;
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}
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@ -3916,6 +4001,7 @@ sk_init_locked(sc_if)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
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reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
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#if 0
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@ -3937,6 +4023,7 @@ sk_init_locked(sc_if)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
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break;
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}
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@ -4010,6 +4097,7 @@ sk_stop(sc_if)
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case SK_YUKON:
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case SK_YUKON_LITE:
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case SK_YUKON_LP:
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case SK_YUKON_EC:
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SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
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SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
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break;
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@ -55,13 +55,23 @@
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#define SK_YUKON 0xB0
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#define SK_YUKON_LITE 0xB1
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#define SK_YUKON_LP 0xB2
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#define SK_YUKON_XL 0xB3
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#define SK_YUKON_EC_U 0xB4
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#define SK_YUKON_EC 0xB6
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#define SK_YUKON_FE 0xB7
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#define SK_YUKON_FAMILY(x) ((x) & 0xB0)
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#define SK_IS_YUKON2(sc) \
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((sc)->sk_type >= SK_YUKON_XL && (sc)->sk_type <= SK_YUKON_FE)
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/* Known revisions in SK_CONFIG. */
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#define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */
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#define SK_YUKON_LITE_REV_A1 0x3
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#define SK_YUKON_LITE_REV_A3 0x7
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#define SK_YUKON_EC_REV_A1 0x0
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#define SK_YUKON_EC_REV_A2 0x1
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#define SK_YUKON_EC_REV_A3 0x2
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/*
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* SysKonnect PCI vendor ID
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*/
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@ -78,6 +88,13 @@
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#define DEVICEID_SK_V1 0x4300
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#define DEVICEID_SK_V2 0x4320
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/*
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* Marvell gigabit ethernet device IDs
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*/
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#define DEVICEID_MRVL_4360 0x4360
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#define DEVICEID_MRVL_4361 0x4361
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#define DEVICEID_MRVL_4362 0x4362
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/*
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* Belkin F5D5005
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*/
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@ -345,8 +362,10 @@
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#define SK_CONFIG 0x011A
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#define SK_CHIPVER 0x011B
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#define SK_EPROM0 0x011C
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#define SK_EPROM1 0x011D
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#define SK_EPROM2 0x011E
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#define SK_EPROM1 0x011D /* yukon/genesis */
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#define SK_Y2_CLKGATE 0x011D /* yukon 2 */
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#define SK_EPROM2 0x011E /* yukon/genesis */
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#define SK_Y2_HWRES 0x011E /* yukon 2 */
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#define SK_EPROM3 0x011F
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#define SK_EP_ADDR 0x0120
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#define SK_EP_DATA 0x0124
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@ -452,6 +471,13 @@
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#define SK_GPIO_DIR8 0x01000000
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#define SK_GPIO_DIR9 0x02000000
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#define SK_Y2_CLKGATE_LINK2_INACTIVE 0x80 /* port 2 inactive */
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#define SK_Y2_HWRES_LINK_1 0x01
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#define SK_Y2_HWRES_LINK_2 0x02
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#define SK_Y2_HWRES_LINK_MASK (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
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#define SK_Y2_HWRES_LINK_DUAL (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
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/* Block 3 Ram interface and MAC arbiter registers */
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#define SK_RAMADDR 0x0180
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#define SK_RAMDATA0 0x0184
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Block a user