Modernize mpc85xx PCI hostbridge driver.
Summary: * Take advantage of NEW_PCIB to remove a lot of setup code. * Fix some bugs related to multiple PCI bridges. There's still room for more cleanup, and still some bugs leftover, but this cleans up a lot. Test Plan: Tested on P5020 board with IDT PCIe switch. Differential Revision: https://reviews.freebsd.org/D4127
This commit is contained in:
Justin Hibbits
parent
a0962bf8bc
commit
fe11dfea79
@ -104,9 +104,9 @@ struct fsl_pcib_softc {
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device_t sc_dev;
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int sc_iomem_target;
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bus_addr_t sc_iomem_alloc, sc_iomem_start, sc_iomem_end;
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bus_addr_t sc_iomem_start, sc_iomem_end;
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int sc_ioport_target;
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bus_addr_t sc_ioport_alloc, sc_ioport_start, sc_ioport_end;
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bus_addr_t sc_ioport_start, sc_ioport_end;
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struct resource *sc_res;
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bus_space_handle_t sc_bsh;
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@ -266,9 +266,8 @@ fsl_pcib_attach(device_t dev)
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/*
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* Scan bus using firmware configured, 0 based bus numbering.
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*/
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sc->sc_busnr = 0;
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maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX;
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sc->sc_busnr = fsl_pcib_init(sc, sc->sc_busnr, maxslot);
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fsl_pcib_init(sc, sc->sc_busnr, maxslot);
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if (sc->sc_pcie) {
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ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
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@ -285,6 +284,7 @@ fsl_pcib_attach(device_t dev)
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return (ofw_pci_attach(dev));
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err:
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//panic("Because I said so\n");
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return (ENXIO);
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}
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@ -294,9 +294,6 @@ fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
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{
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uint32_t addr, data;
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if (bus == sc->sc_busnr - 1)
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bus = 0;
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addr = CONFIG_ACCESS_ENABLE;
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addr |= (bus & 0xff) << 16;
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addr |= (slot & 0x1f) << 11;
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@ -335,9 +332,6 @@ fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
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{
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uint32_t addr;
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if (bus == sc->sc_busnr - 1)
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bus = 0;
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addr = CONFIG_ACCESS_ENABLE;
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addr |= (bus & 0xff) << 16;
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addr |= (slot & 0x1f) << 11;
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@ -448,65 +442,6 @@ fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus,
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}
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}
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static int
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fsl_pcib_init_bar(struct fsl_pcib_softc *sc, int bus, int slot, int func,
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int barno)
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{
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bus_addr_t *allocp;
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uint32_t addr, mask, size;
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int reg, width;
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reg = PCIR_BAR(barno);
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if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) {
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switch (barno) {
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case 0: addr = 0x1f0; break;
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case 1: addr = 0x3f4; break;
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case 2: addr = 0x170; break;
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case 3: addr = 0x374; break;
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case 4: addr = 0xcc0; break;
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default: return (1);
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}
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
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return (1);
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}
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
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size = fsl_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
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if (size == 0)
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return (1);
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width = ((size & 7) == 4) ? 2 : 1;
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if (size & 1) { /* I/O port */
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allocp = &sc->sc_ioport_alloc;
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size &= ~3;
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if ((size & 0xffff0000) == 0)
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size |= 0xffff0000;
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} else { /* memory */
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allocp = &sc->sc_iomem_alloc;
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size &= ~15;
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}
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mask = ~size;
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size = mask + 1;
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/* Sanity check (must be a power of 2). */
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if (size & mask)
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return (width);
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addr = (*allocp + mask) & ~mask;
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*allocp = addr + size;
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if (bootverbose)
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printf("PCI %u:%u:%u:%u: reg %x: size=%08x: addr=%08x\n",
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device_get_unit(sc->sc_dev), bus, slot, func, reg,
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size, addr);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
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if (width == 2)
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
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0, 4);
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return (width);
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}
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static int
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fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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{
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@ -514,9 +449,8 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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int old_pribus, old_secbus, old_subbus;
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int new_pribus, new_secbus, new_subbus;
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int slot, func, maxfunc;
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int bar, maxbar;
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uint16_t vendor, device;
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uint8_t command, hdrtype, class, subclass;
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uint8_t command, hdrtype, subclass;
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secbus = bus;
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for (slot = 0; slot <= maxslot; slot++) {
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@ -550,26 +484,9 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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if (vendor == 0x1106)
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fsl_pcib_init_via(sc, device, bus, slot, func);
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/* Program the base address registers. */
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maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6;
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bar = 0;
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while (bar < maxbar)
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bar += fsl_pcib_init_bar(sc, bus, slot, func,
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bar);
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/* Put a placeholder interrupt value */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_INTLINE, PCI_INVALID_IRQ, 1);
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command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_COMMAND, command, 1);
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/*
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* Handle PCI-PCI bridges
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*/
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class = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_CLASS, 1);
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subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_SUBCLASS, 1);
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@ -579,32 +496,6 @@ fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot)
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secbus++;
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/* Program I/O decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOBASEL_1, sc->sc_ioport_start >> 8, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOLIMITL_1, sc->sc_ioport_end >> 8, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOBASEH_1, sc->sc_ioport_start >> 16, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOLIMITH_1, sc->sc_ioport_end >> 16, 2);
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/* Program (non-prefetchable) memory decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_MEMBASE_1, sc->sc_iomem_start >> 16, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_MEMLIMIT_1, sc->sc_iomem_end >> 16, 2);
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/* Program prefetchable memory decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMBASEL_1, 0x0010, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMLIMITL_1, 0x000f, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMBASEH_1, 0x00000000, 4);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMLIMITH_1, 0x00000000, 4);
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/* Read currect bus register configuration */
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old_pribus = fsl_pcib_read_config(sc->sc_dev, bus,
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slot, func, PCIR_PRIBUS_1, 1);
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@ -678,10 +569,10 @@ fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start,
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switch (res) {
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case SYS_RES_MEMORY:
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attr = 0x80044000 | (ffsl(size) - 2);
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attr = 0x80044000 | (ffsll(size) - 2);
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break;
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case SYS_RES_IOPORT:
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attr = 0x80088000 | (ffsl(size) - 2);
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attr = 0x80088000 | (ffsll(size) - 2);
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break;
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default:
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attr = 0x0004401f;
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@ -785,7 +676,6 @@ fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
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sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci;
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sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci +
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sc->pci_sc.sc_range[i].size - 1;
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sc->sc_ioport_alloc = 0x1000 + sc->pci_sc.sc_range[i].pci;
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break;
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case OFW_PCI_PHYS_HI_SPACE_MEM32:
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case OFW_PCI_PHYS_HI_SPACE_MEM64:
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@ -797,7 +687,6 @@ fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
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sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci;
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sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci +
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sc->pci_sc.sc_range[i].size - 1;
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sc->sc_iomem_alloc = sc->pci_sc.sc_range[i].pci;
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break;
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default:
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panic("Unknown range type %#x\n",
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@ -59,6 +59,7 @@ __FBSDID("$FreeBSD$");
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static int
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fsl_pcib_rc_probe(device_t dev)
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{
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if (pci_get_vendor(dev) != 0x1957)
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return (ENXIO);
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if (pci_get_progif(dev) != 0)
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@ -71,28 +72,8 @@ fsl_pcib_rc_probe(device_t dev)
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return (BUS_PROBE_DEFAULT);
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}
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static int
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fsl_pcib_rc_attach(device_t dev)
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{
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struct pcib_softc *sc;
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device_t child;
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pcib_bridge_init(dev);
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pcib_attach_common(dev);
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sc = device_get_softc(dev);
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if (sc->bus.sec != 0) {
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child = device_add_child(dev, "pci", -1);
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if (child != NULL)
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return (bus_generic_attach(dev));
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}
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return (0);
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}
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static device_method_t fsl_pcib_rc_methods[] = {
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DEVMETHOD(device_probe, fsl_pcib_rc_probe),
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DEVMETHOD(device_attach, fsl_pcib_rc_attach),
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DEVMETHOD_END
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};
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