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Replace mips/sentry5 with mips/broadcom

Browse Source 
The delta between SENTRY5 and BCM was already small due to BCM being
derived from SENTRY5; re-integrating the two avoids the maintenance
overhead of keeping them both in sync with bhnd(4) changes.


- Re-integrate minor SENTRY5 deltas in bcm_machdep.c
- Modify uart_cpu_chipc to allow specifying UART debug/console flags via
  kenv and device hints.
- Switch SENTRY5 to std.broadcom
- Enabled CFI flash support for SENTRY5

Reviewed by:	Michael Zhilin <mizkha@gmail.com> (Broadcom MIPS support)
Approved by:	re (gjb), adrian (mentor)
Differential Revision:	https://reviews.freebsd.org/D6897
This commit is contained in:
Landon J. Fuller 2016-06-25 04:34:54 +00:00
parent 0c91e8927d
commit ff29b85a34
21 changed files with 145 additions and 789 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sys/mips/atheros/ar71xx_chip.c
View File

@ -55,8 +55,6 @@ __FBSDID("$FreeBSD$");
#include <mips/atheros/ar71xx_chip.h>
#include <mips/atheros/ar71xx_cpudef.h>
#include <mips/sentry5/s5reg.h>
/* XXX these should replace the current definitions in ar71xxreg.h */
/* XXX perhaps an ar71xx_chip.h header file? */
#define AR71XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00

2
sys/mips/atheros/ar71xx_machdep.c
View File

@ -58,8 +58,6 @@ __FBSDID("$FreeBSD$");
#include <mips/atheros/ar71xx_cpudef.h>
#include <mips/atheros/ar71xx_macaddr.h>
#include <mips/sentry5/s5reg.h>
extern char edata[], end[];
/* 4KB static data aread to keep a copy of the bootload env until

2
sys/mips/atheros/ar724x_chip.c
View File

@ -59,8 +59,6 @@ __FBSDID("$FreeBSD$");
#include <mips/atheros/ar71xx_chip.h>
#include <mips/atheros/ar724x_chip.h>
#include <mips/sentry5/s5reg.h>
static void
ar724x_chip_detect_mem_size(void)
{

2
sys/mips/atheros/ar91xx_chip.c
View File

@ -57,8 +57,6 @@ __FBSDID("$FreeBSD$");
#include <mips/atheros/ar91xxreg.h>
#include <mips/atheros/ar91xx_chip.h>
#include <mips/sentry5/s5reg.h>
static void
ar91xx_chip_detect_mem_size(void)
{

81
sys/mips/broadcom/bcm_machdep.c
View File

@ -71,7 +71,6 @@ __FBSDID("$FreeBSD$");
#include <machine/trap.h>
#include <machine/vmparam.h>
#include <mips/sentry5/s5reg.h>
#include "bcm_socinfo.h"
#ifdef CFE
@ -79,7 +78,9 @@ __FBSDID("$FreeBSD$");
#endif
#if 0
#define BROADCOM_TRACE 0
#define BCM_TRACE(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
#else
#define BCM_TRACE(_fmt, ...)
#endif
extern int *edata;
@ -109,16 +110,12 @@ mips_init(void)
result = cfe_enummem(i / 2, 0, &addr, &len, &type);
if (result < 0) {
#ifdef BROADCOM_TRACE
printf("There is no phys memory for: %d\n", i);
#endif
BCM_TRACE("There is no phys memory for: %d\n", i);
phys_avail[i] = phys_avail[i + 1] = 0;
break;
}
if (type != CFE_MI_AVAILABLE){
#ifdef BROADCOM_TRACE
printf("phys memory is not available: %d\n", i);
#endif
if (type != CFE_MI_AVAILABLE) {
BCM_TRACE("phys memory is not available: %d\n", i);
continue;
}
@ -131,19 +128,16 @@ mips_init(void)
*/
phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
}
#ifdef BROADCOM_TRACE
printf("phys memory is available for: %d\n", i);
printf(" => addr = %jx\n", addr);
printf(" => len = %jd\n", len);
#endif
BCM_TRACE("phys memory is available for: %d\n", i);
BCM_TRACE(" => addr = %jx\n", addr);
BCM_TRACE(" => len = %jd\n", len);
phys_avail[i + 1] = addr + len;
physmem += len;
}
#ifdef BROADCOM_TRACE
printf("Total phys memory is : %ld\n", physmem);
#endif
BCM_TRACE("Total phys memory is : %ld\n", physmem);
realmem = btoc(physmem);
#endif
@ -165,15 +159,25 @@ mips_init(void)
#endif
}
#define BCM_REG_CHIPC 0x18000000
void
platform_reset(void)
{
printf("bcm::platform_reset()\n");
intr_disable();
#if defined(CFE)
cfe_exit(0, 0);
#else
/* PMU watchdog reset */
BCM_WRITE_REG32(BCM_REG_CHIPC_PMUWD_OFFS, 2); /* PMU watchdog */
#endif
#if 0
/* Non-PMU reset
* XXX: Need chipc capability flags */
*((volatile uint8_t *)MIPS_PHYS_TO_KSEG1(SENTRY5_EXTIFADR)) = 0x80;
#endif
for (;;);
}
@ -194,6 +198,37 @@ platform_start(__register_t a0, __register_t a1, __register_t a2,
/* Initialize pcpu stuff */
mips_pcpu0_init();
#if 0
/*
* Probe the Broadcom on-chip PLL clock registers
* and discover the CPU pipeline clock and bus clock
* multipliers from this.
* XXX: Wrong place. You have to ask the ChipCommon
* or External Interface cores on the SiBa.
*/
uint32_t busmult, cpumult, refclock, clkcfg1;
#define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F
#define S5_CLKCFG1_BUSMULT_MASK 0x000003E0
#define S5_CLKCFG1_BUSMULT_SHIFT 5
#define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00
#define S5_CLKCFG1_CPUMULT_SHIFT 10
counter_freq = 100000000; /* XXX */
clkcfg1 = s5_rd_clkcfg1();
printf("clkcfg1 = 0x%08x\n", clkcfg1);
refclock = clkcfg1 & 0x1F;
busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1;
cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1;
printf("refclock = %u\n", refclock);
printf("busmult = %u\n", busmult);
printf("cpumult = %u\n", cpumult);
counter_freq = cpumult * refclock;
#endif
socinfo = bcm_get_socinfo();
platform_counter_freq = socinfo->cpurate * 1000 * 1000; /* BCM4718 is 480MHz */
@ -212,10 +247,10 @@ platform_start(__register_t a0, __register_t a1, __register_t a2,
if (a3 == CFE_EPTSEAL)
cfe_init(a0, a2);
#endif
cninit();
mips_init();
/* BCM471x timer is 1/2 of Clk */
mips_timer_init_params(platform_counter_freq, 1);
mips_timer_init_params(platform_counter_freq, socinfo->double_count);
}

25
sys/mips/broadcom/bcm_socinfo.c
View File

@ -33,22 +33,23 @@ __FBSDID("$FreeBSD$");
/* found on https://wireless.wiki.kernel.org/en/users/drivers/b43/soc */
struct bcm_socinfo bcm_socinfos[] = {
{0x00005300, 600, 25000000}, /* BCM4706 to check */
{0x0022B83A, 300, 20000000}, /* BCM4716B0 ASUS RT-N12 */
{0x00914716, 354, 20000000}, /* BCM4717A1 to check */
{0x00A14716, 480, 20000000}, /* BCM4718A1 ASUS RT-N16 */
{0x00435356, 300, 25000000}, /* BCM5356A1 (RT-N10, WNR1000v3) */
{0x00825357, 500, 20000000}, /* BCM5358UB0 ASUS RT-N53A1 */
{0x00845357, 300, 20000000}, /* BCM5357B0 to check */
{0x00945357, 500, 20000000}, /* BCM5358 */
{0x00A45357, 500, 20000000}, /* BCM47186B0 Tenda N60 */
{0x0085D144, 300, 20000000}, /* BCM5356C0 */
{0x00B5D144, 300, 20000000}, /* BCM5357C0 */
{0x00005300, 600, 25000000, 1}, /* BCM4706 to check */
{0x0022B83A, 300, 20000000, 1}, /* BCM4716B0 ASUS RT-N12 */
{0x00914716, 354, 20000000, 1}, /* BCM4717A1 to check */
{0x00A14716, 480, 20000000, 1}, /* BCM4718A1 ASUS RT-N16 */
{0x00435356, 300, 25000000, 1}, /* BCM5356A1 (RT-N10, WNR1000v3) */
{0x00825357, 500, 20000000, 1}, /* BCM5358UB0 ASUS RT-N53A1 */
{0x00845357, 300, 20000000, 1}, /* BCM5357B0 to check */
{0x00945357, 500, 20000000, 1}, /* BCM5358 */
{0x00A45357, 500, 20000000, 1}, /* BCM47186B0 Tenda N60 */
{0x0085D144, 300, 20000000, 1}, /* BCM5356C0 */
{0x00B5D144, 300, 20000000, 1}, /* BCM5357C0 */
{0x00015365, 200, 0, 1}, /* BCM5365 */
{0,0,0}
};
/* Most popular BCM SoC info */
struct bcm_socinfo BCM_DEFAULT_SOCINFO = {0x0, 300, 20000000};
struct bcm_socinfo BCM_DEFAULT_SOCINFO = {0x0, 300, 20000000, 0};
struct bcm_socinfo*
bcm_get_socinfo_by_socid(uint32_t key)

7
sys/mips/broadcom/bcm_socinfo.h
View File

@ -35,9 +35,10 @@
#include <machine/cpuregs.h>
struct bcm_socinfo {
uint32_t id;
uint32_t cpurate; /* in MHz */
uint32_t uartrate; /* in Hz */
uint32_t id;
uint32_t cpurate; /* in MHz */
uint32_t uartrate; /* in Hz */
int double_count;
};
struct bcm_socinfo* bcm_get_socinfo_by_socid(uint32_t key);

4
sys/mips/broadcom/std.broadcom
View File

@ -3,5 +3,7 @@
machine mips mipsel
cpu CPU_MIPS74K
makeoptions INTRNG
options INTRNG
files "../broadcom/files.broadcom"

65
sys/mips/broadcom/uart_cpu_chipc.c
View File

@ -39,6 +39,8 @@ __FBSDID("$FreeBSD$");
#include <machine/bus.h>
#include <dev/bhnd/cores/chipc/chipcreg.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_cpu.h>
@ -48,31 +50,74 @@ __FBSDID("$FreeBSD$");
bus_space_tag_t uart_bus_space_io;
bus_space_tag_t uart_bus_space_mem;
static struct uart_class *chipc_uart_class = &uart_ns8250_class;
#define CHIPC_UART_BAUDRATE 115200
int
uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
{
return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
}
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
static int
uart_cpu_init(struct uart_devinfo *di, int uart, int baudrate)
{
struct uart_class *class;
struct bcm_socinfo *socinfo;
if (uart >= CHIPC_UART_MAX)
return (EINVAL);
socinfo = bcm_get_socinfo();
class = &uart_ns8250_class;
di->ops = uart_getops(class);
di->ops = uart_getops(chipc_uart_class);
di->bas.chan = 0;
di->bas.bst = mips_bus_space_generic;
di->bas.bsh = (bus_space_handle_t)BCM_SOCREG(BCM_REG_CHIPC_UART);
di->bas.bst = uart_bus_space_mem;
di->bas.bsh = (bus_space_handle_t) BCM_SOCREG(CHIPC_UART(uart));
di->bas.regshft = 0;
di->bas.rclk = socinfo->uartrate; /* in Hz */
di->baudrate = 115200;
di->baudrate = baudrate;
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
uart_bus_space_io = NULL;
uart_bus_space_mem = mips_bus_space_generic;
return (0);
}
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
int ivar;
uart_bus_space_io = NULL;
uart_bus_space_mem = mips_bus_space_generic;
/* Check the environment. */
if (uart_getenv(devtype, di, chipc_uart_class) == 0)
return (0);
/* Scan the device hints for the first matching device */
for (int i = 0; i < CHIPC_UART_MAX; i++) {
if (resource_int_value("uart", i, "flags", &ivar))
continue;
/* Check usability */
if (devtype == UART_DEV_CONSOLE && !UART_FLAGS_CONSOLE(ivar))
continue;
if (devtype == UART_DEV_DBGPORT && !UART_FLAGS_DBGPORT(ivar))
continue;
if (resource_int_value("uart", i, "disabled", &ivar) == 0 &&
ivar == 0)
continue;
/* Found */
if (resource_int_value("uart", i, "baud", &ivar) != 0)
ivar = CHIPC_UART_BAUDRATE;
return (uart_cpu_init(di, i, ivar));
}
/* Default to uart0/115200 */
return (uart_cpu_init(di, 0, CHIPC_UART_BAUDRATE));
}

4
sys/mips/conf/BCM
View File

@ -6,6 +6,7 @@
#
ident BCM
cpu CPU_MIPS74K
hints "BCM.hints"
include "../broadcom/std.broadcom"
@ -16,9 +17,6 @@ options ALT_BREAK_TO_DEBUGGER
options BREAK_TO_DEBUGGER
options BOOTVERBOSE=0
makeoptions INTRNG
options INTRNG
makeoptions TRAMPLOADADDR=0x80800000
makeoptions DEBUG="-g3" #Build kernel with gdb(1) debug symbols
makeoptions MODULES_OVERRIDE=""

1
sys/mips/conf/BCM.hints
View File

@ -2,4 +2,3 @@
hint.bhnd.0.at="nexus0"
hint.bhnd.0.maddr="0x18000000"
hint.bhnd.0.msize="0x00100000"

13
sys/mips/conf/SENTRY5
View File

@ -25,11 +25,11 @@
#
ident SENTRY5
cpu CPU_MIPS4KC
makeoptions TRAMPLOADADDR=0x807963c0
# XXX only siba should be hardwired for now; we will use
# bus enumeration there
hints "SENTRY5.hints"
include "../sentry5/std.sentry5"
include "../broadcom/std.broadcom"
# sentry5 normally ships with cfe firmware; use the console for now
options CFE
@ -78,11 +78,10 @@ device usb # USB Bus (required)
device uhci # UHCI PCI->USB interface
device ehci # EHCI PCI->USB interface (USB 2.0)
# need to teach the code to ignore the bridge....
device cfi # parallel flash
device cfid
# XXX notyet; need to be auto probed children of siba_cc.
#device uart
device uart
device loop
device ether

8
sys/mips/conf/SENTRY5.hints
View File

@ -1,5 +1,7 @@
# $FreeBSD$
hint.bhnd.0.at="nexus0"
hint.bhnd.0.maddr="0x18000000"
hint.bhnd.0.msize="0x1000"
# XXX irq?
hint.bhnd.0.maddr="0x18000000"
hint.bhnd.0.msize="0x00100000"
# console on uart1
hint.uart.1.flags="0x10"

9
sys/mips/sentry5/files.sentry5
View File

@ -1,9 +0,0 @@
# $FreeBSD$
# TODO: Add attachment elsehwere in the tree
# for USB 1.1 OHCI, Ethernet and IPSEC cores
# which are believed to be devices we have drivers for
# which just need to be tweaked for attachment to an SSB system bus.
mips/sentry5/s5_machdep.c standard
mips/mips/intr_machdep.c standard
mips/mips/tick.c standard

183
sys/mips/sentry5/obio.c
View File

@ -1,183 +0,0 @@
/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */
/*-
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* On-board device autoconfiguration support for Broadcom Sentry5
* based boards.
* XXX This is totally bogus and is just enough to get the console hopefully
* running on the sentry5.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <sys/malloc.h>
#include <machine/bus.h>
#include <mips/sentry5/obiovar.h>
#include <mips/sentry5/sentry5reg.h>
int obio_probe(device_t);
int obio_attach(device_t);
/*
* A bit tricky and hackish. Since we need OBIO to rely
* on PCI we make it pseudo-pci device. But there should
* be only one such device, so we use this static flag
* to prevent false positives on every realPCI device probe.
*/
static int have_one = 0;
int
obio_probe(device_t dev)
{
if (!have_one) {
have_one = 1;
return 0;
}
return (ENXIO);
}
int
obio_attach(device_t dev)
{
struct obio_softc *sc = device_get_softc(dev);
sc->oba_st = MIPS_BUS_SPACE_IO;
sc->oba_addr = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
sc->oba_size = 0x03FFFFFF; /* XXX sb pci bus 0 aperture size? */
sc->oba_rman.rm_type = RMAN_ARRAY;
sc->oba_rman.rm_descr = "OBIO I/O";
if (rman_init(&sc->oba_rman) != 0 ||
rman_manage_region(&sc->oba_rman,
sc->oba_addr, sc->oba_addr + sc->oba_size) != 0)
panic("obio_attach: failed to set up I/O rman");
sc->oba_irq_rman.rm_type = RMAN_ARRAY;
sc->oba_irq_rman.rm_descr = "OBIO IRQ";
/*
* This module is intended for UART purposes only and
* it's IRQ is 4
*/
if (rman_init(&sc->oba_irq_rman) != 0 ||
rman_manage_region(&sc->oba_irq_rman, 4, 4) != 0)
panic("obio_attach: failed to set up IRQ rman");
device_add_child(dev, "uart", 0);
bus_generic_probe(dev);
bus_generic_attach(dev);
return (0);
}
static struct resource *
obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
{
struct resource *rv;
struct rman *rm;
bus_space_handle_t bh = 0;
struct obio_softc *sc = device_get_softc(bus);
switch (type) {
case SYS_RES_IRQ:
rm = &sc->oba_irq_rman;
break;
case SYS_RES_MEMORY:
return (NULL);
case SYS_RES_IOPORT:
rm = &sc->oba_rman;
bh = sc->oba_addr;
start = bh;
break;
default:
return (NULL);
}
rv = rman_reserve_resource(rm, start, end, count, flags, child);
if (rv == NULL)
return (NULL);
if (type == SYS_RES_IRQ)
return (rv);
rman_set_rid(rv, *rid);
rman_set_bustag(rv, mips_bus_space_generic);
rman_set_bushandle(rv, bh);
if (0) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
return (rv);
}
static int
obio_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
return (0);
}
static device_method_t obio_methods[] = {
DEVMETHOD(device_probe, obio_probe),
DEVMETHOD(device_attach, obio_attach),
DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
DEVMETHOD(bus_activate_resource, obio_activate_resource),
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
{0, 0},
};
static driver_t obio_driver = {
"obio",
obio_methods,
sizeof(struct obio_softc),
};
static devclass_t obio_devclass;
DRIVER_MODULE(obio, pci, obio_driver, obio_devclass, 0, 0);

58
sys/mips/sentry5/obiovar.h
View File

@ -1,58 +0,0 @@
/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */
/*-
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _SENTRY5_OBIOVAR_H_
#define _SENTRY5_OBIOVAR_H_
#include <sys/rman.h>
struct obio_softc {
bus_space_tag_t oba_st; /* bus space tag */
bus_addr_t oba_addr; /* address of device */
bus_size_t oba_size; /* size of device */
int oba_width; /* bus width */
int oba_irq; /* XINT interrupt bit # */
struct rman oba_rman;
struct rman oba_irq_rman;
};
extern struct bus_space obio_bs_tag;
#endif /* _SENTRY5_OBIOVAR_H_ */

223
sys/mips/sentry5/s5_machdep.c
View File

@ -1,223 +0,0 @@
/*-
* Copyright (c) 2007 Bruce M. Simpson.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/imgact.h>
#include <sys/bio.h>
#include <sys/buf.h>
#include <sys/bus.h>
#include <sys/cpu.h>
#include <sys/cons.h>
#include <sys/exec.h>
#include <sys/ucontext.h>
#include <sys/proc.h>
#include <sys/kdb.h>
#include <sys/ptrace.h>
#include <sys/reboot.h>
#include <sys/signalvar.h>
#include <sys/sysent.h>
#include <sys/sysproto.h>
#include <sys/user.h>
#include <vm/vm.h>
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <machine/cache.h>
#include <machine/clock.h>
#include <machine/cpu.h>
#include <machine/cpuinfo.h>
#include <machine/cpufunc.h>
#include <machine/cpuregs.h>
#include <machine/hwfunc.h>
#include <machine/intr_machdep.h>
#include <machine/locore.h>
#include <machine/md_var.h>
#include <machine/pte.h>
#include <machine/sigframe.h>
#include <machine/trap.h>
#include <machine/vmparam.h>
#include <mips/sentry5/s5reg.h>
#ifdef CFE
#include <dev/cfe/cfe_api.h>
#endif
extern int *edata;
extern int *end;
void
platform_cpu_init()
{
/* Nothing special */
}
static void
mips_init(void)
{
int i, j;
printf("entry: mips_init()\n");
#ifdef CFE
/*
* Query DRAM memory map from CFE.
*/
physmem = 0;
for (i = 0; i < 10; i += 2) {
int result;
uint64_t addr, len, type;
result = cfe_enummem(i, 0, &addr, &len, &type);
if (result < 0) {
phys_avail[i] = phys_avail[i + 1] = 0;
break;
}
if (type != CFE_MI_AVAILABLE)
continue;
phys_avail[i] = addr;
if (i == 0 && addr == 0) {
/*
* If this is the first physical memory segment probed
* from CFE, omit the region at the start of physical
* memory where the kernel has been loaded.
*/
phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
}
phys_avail[i + 1] = addr + len;
physmem += len;
}
realmem = btoc(physmem);
#endif
for (j = 0; j < i; j++)
dump_avail[j] = phys_avail[j];
physmem = realmem;
init_param1();
init_param2(physmem);
mips_cpu_init();
pmap_bootstrap();
mips_proc0_init();
mutex_init();
kdb_init();
#ifdef KDB
if (boothowto & RB_KDB)
kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
#endif
}
void
platform_reset(void)
{
#if defined(CFE)
cfe_exit(0, 0);
#else
*((volatile uint8_t *)MIPS_PHYS_TO_KSEG1(SENTRY5_EXTIFADR)) = 0x80;
#endif
}
void
platform_start(__register_t a0, __register_t a1, __register_t a2,
__register_t a3)
{
vm_offset_t kernend;
uint64_t platform_counter_freq;
/* clear the BSS and SBSS segments */
kernend = (vm_offset_t)&end;
memset(&edata, 0, kernend - (vm_offset_t)(&edata));
mips_postboot_fixup();
/* Initialize pcpu stuff */
mips_pcpu0_init();
#ifdef CFE
/*
* Initialize CFE firmware trampolines before
* we initialize the low-level console.
*
* CFE passes the following values in registers:
* a0: firmware handle
* a2: firmware entry point
* a3: entry point seal
*/
if (a3 == CFE_EPTSEAL)
cfe_init(a0, a2);
#endif
cninit();
mips_init();
# if 0
/*
* Probe the Broadcom Sentry5's on-chip PLL clock registers
* and discover the CPU pipeline clock and bus clock
* multipliers from this.
* XXX: Wrong place. You have to ask the ChipCommon
* or External Interface cores on the SiBa.
*/
uint32_t busmult, cpumult, refclock, clkcfg1;
#define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F
#define S5_CLKCFG1_BUSMULT_MASK 0x000003E0
#define S5_CLKCFG1_BUSMULT_SHIFT 5
#define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00
#define S5_CLKCFG1_CPUMULT_SHIFT 10
counter_freq = 100000000; /* XXX */
clkcfg1 = s5_rd_clkcfg1();
printf("clkcfg1 = 0x%08x\n", clkcfg1);
refclock = clkcfg1 & 0x1F;
busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1;
cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1;
printf("refclock = %u\n", refclock);
printf("busmult = %u\n", busmult);
printf("cpumult = %u\n", cpumult);
counter_freq = cpumult * refclock;
# else
platform_counter_freq = 200 * 1000 * 1000; /* Sentry5 is 200MHz */
# endif
mips_timer_init_params(platform_counter_freq, 0);
}

58
sys/mips/sentry5/s5reg.h
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@ -1,58 +0,0 @@
/* $FreeBSD$ */
#ifndef _MIPS32_SENTRY5_SENTRY5REG_H_
#define _MIPS32_SENTRY5_SENTRY5REG_H_
#define SENTRY5_UART0ADR 0x18000300
#define SENTRY5_UART1ADR 0x18000400
/* Reset register implemented here in a PLD device. */
#define SENTRY5_EXTIFADR 0x1F000000
#define SENTRY5_DORESET 0x80
/*
* Custom CP0 register macros.
* XXX: This really needs the mips cpuregs.h file for the barrier.
*/
#define S5_RDRW32_C0P0_CUST22(n,r) \
static __inline u_int32_t \
s5_rd_ ## n (void) \
{ \
int v0; \
__asm __volatile ("mfc0 %[v0], $22, "__XSTRING(r)" ;" \
: [v0] "=&r"(v0)); \
/*mips_barrier();*/ \
return (v0); \
} \
static __inline void \
s5_wr_ ## n (u_int32_t a0) \
{ \
__asm __volatile ("mtc0 %[a0], $22, "__XSTRING(r)" ;" \
__XSTRING(COP0_SYNC)";" \
"nop;" \
"nop;" \
: \
: [a0] "r"(a0)); \
/*mips_barrier();*/ \
} struct __hack
/*
* All 5 of these sub-registers are used by Linux.
* There is a further custom register at 25 which is not used.
*/
#define S5_CP0_DIAG 0
#define S5_CP0_CLKCFG1 1
#define S5_CP0_CLKCFG2 2
#define S5_CP0_SYNC 3
#define S5_CP0_CLKCFG3 4
#define S5_CP0_RESET 5
/* s5_[rd|wr]_xxx() */
S5_RDRW32_C0P0_CUST22(diag, S5_CP0_DIAG);
S5_RDRW32_C0P0_CUST22(clkcfg1, S5_CP0_CLKCFG1);
S5_RDRW32_C0P0_CUST22(clkcfg2, S5_CP0_CLKCFG2);
S5_RDRW32_C0P0_CUST22(sync, S5_CP0_SYNC);
S5_RDRW32_C0P0_CUST22(clkcfg3, S5_CP0_CLKCFG3);
S5_RDRW32_C0P0_CUST22(reset, S5_CP0_RESET);
#endif /* _MIPS32_SENTRY5_SENTRY5REG_H_ */

10
sys/mips/sentry5/std.sentry5
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@ -1,10 +0,0 @@
# $FreeBSD$
#
machine mips mipsel
cpu CPU_MIPS4KC
options CPU_SENTRY5 # XXX should this be a
# sub-cpu option?
files "../sentry5/files.sentry5"

95
sys/mips/sentry5/uart_bus_sbusart.c
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@ -1,95 +0,0 @@
/*-
* Copyright (c) 2007 Bruce M. Simpson.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* $Id$
*/
/*
* Skeleton of this file was based on respective code for ARM
* code written by Olivier Houchard.
*/
/*
* XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
* experimental and was written for MIPS32 port.
*/
#include "opt_uart.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h>
#include <dev/pci/pcivar.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_cpu.h>
#include <mips/sentry5/sentry5reg.h>
#include "uart_if.h"
static int uart_malta_probe(device_t dev);
extern struct uart_class malta_uart_class;
static device_method_t uart_malta_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, uart_malta_probe),
DEVMETHOD(device_attach, uart_bus_attach),
DEVMETHOD(device_detach, uart_bus_detach),
{ 0, 0 }
};
static driver_t uart_malta_driver = {
uart_driver_name,
uart_malta_methods,
sizeof(struct uart_softc),
};
extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
static int
uart_malta_probe(device_t dev)
{
struct uart_softc *sc;
sc = device_get_softc(dev);
sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
sc->sc_class = &uart_ns8250_class;
bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
sc->sc_sysdev->bas.bst = mips_bus_space_generic;
sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
sc->sc_bas.bst = mips_bus_space_generic;
sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
return(uart_bus_probe(dev, 0, 0, 0, 0));
}
DRIVER_MODULE(uart, obio, uart_malta_driver, uart_devclass, 0, 0);

82
sys/mips/sentry5/uart_cpu_sbusart.c
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@ -1,82 +0,0 @@
/*-
* Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
*/
/*
* Skeleton of this file was based on respective code for ARM
* code written by Olivier Houchard.
*/
/*
* XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
* experimental and was written for MIPS32 port.
*/
#include "opt_uart.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/cons.h>
#include <machine/bus.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_cpu.h>
#include <mips/sentry5/sentry5reg.h>
bus_space_tag_t uart_bus_space_io;
bus_space_tag_t uart_bus_space_mem;
extern struct uart_ops malta_usart_ops;
extern struct bus_space malta_bs_tag;
int
uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
{
return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
}
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = 0;
di->bas.regshft = 0;
di->bas.rclk = 0;
di->baudrate = 115200;
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
uart_bus_space_io = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
uart_bus_space_mem = mips_bus_space_generic;
di->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR);
return (0);
}