Merge the 1 and 2 byte versions of the atomic functions into one.
After pushing in my fix for the 2 byte functions, I realized that the functions for 1 and 2 byte operations had become identical. Reduce the code size by merging the functions for 1 and 2 byte operations together. While there, slightly improve variable naming and comments.
This commit is contained in:
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parent
f8eb20d5ba
commit
ff6873b414
@ -75,6 +75,11 @@ typedef union {
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uint32_t v32;
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} reg_t;
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/*
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* Given a memory address pointing to an 8-bit or 16-bit integer, return
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* the address of the 32-bit word containing it.
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*/
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static inline uint32_t *
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round_to_word(void *ptr)
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{
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@ -83,7 +88,9 @@ round_to_word(void *ptr)
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}
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/*
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* 8-bit routines.
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* Utility functions for loading and storing 8-bit and 16-bit integers
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* in 32-bit words at an offset corresponding with the location of the
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* atomic variable.
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*/
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static inline void
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@ -104,132 +111,6 @@ get_1(const reg_t *r, uint8_t *offset_ptr)
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return (r->v8[offset]);
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}
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uint8_t
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__sync_lock_test_and_set_1(uint8_t *mem8, uint8_t val8)
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{
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uint32_t *mem32;
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reg_t val32, negmask32, old;
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uint32_t temp;
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mem32 = round_to_word(mem8);
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val32.v32 = 0x00000000;
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put_1(&val32, mem8, val8);
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negmask32.v32 = 0xffffffff;
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put_1(&negmask32, mem8, val8);
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mips_sync();
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__asm volatile (
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"1:"
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"\tll %0, %5\n" /* Load old value. */
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"\tand %2, %4, %0\n" /* Trim out affected part. */
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"\tor %2, %3\n" /* Put in the new value. */
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"\tsc %2, %1\n" /* Attempt to store. */
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"\tbeqz %2, 1b\n" /* Spin if failed. */
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp)
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: "r" (val32.v32), "r" (negmask32.v32), "m" (*mem32));
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return (get_1(&old, mem8));
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}
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uint8_t
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__sync_val_compare_and_swap_1(uint8_t *mem8, uint8_t expected, uint8_t desired)
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{
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uint32_t *mem32;
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reg_t expected32, desired32, posmask32, negmask32, old;
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uint32_t temp;
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mem32 = round_to_word(mem8);
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expected32.v32 = 0x00000000;
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put_1(&expected32, mem8, expected);
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desired32.v32 = 0x00000000;
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put_1(&desired32, mem8, desired);
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posmask32.v32 = 0x00000000;
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put_1(&posmask32, mem8, 0xff);
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negmask32.v32 = ~posmask32.v32;
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mips_sync();
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__asm volatile (
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"1:"
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"\tll %0, %7\n" /* Load old value. */
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"\tand %2, %5, %0\n" /* Isolate affected part. */
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"\tbne %2, %3, 2f\n" /* Compare to expected value. */
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"\tand %2, %6, %0\n" /* Trim out affected part. */
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"\tor %2, %4\n" /* Put in the new value. */
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"\tsc %2, %1\n" /* Attempt to store. */
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"\tbeqz %2, 1b\n" /* Spin if failed. */
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"2:"
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: "=&r" (old), "=m" (*mem32), "=&r" (temp)
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: "r" (expected32.v32), "r" (desired32.v32),
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"r" (posmask32.v32), "r" (negmask32.v32), "m" (*mem32));
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return (get_1(&old, mem8));
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}
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#define EMIT_ARITHMETIC_FETCH_AND_OP_1(name, op) \
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uint8_t \
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__sync_##name##_1(uint8_t *mem8, uint8_t val8) \
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{ \
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uint32_t *mem32; \
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reg_t val32, posmask32, negmask32, old; \
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uint32_t temp1, temp2; \
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\
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mem32 = round_to_word(mem8); \
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val32.v32 = 0x00000000; \
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put_1(&val32, mem8, val8); \
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posmask32.v32 = 0x00000000; \
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put_1(&posmask32, mem8, 0xff); \
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negmask32.v32 = ~posmask32.v32; \
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\
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mips_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %7\n" /* Load old value. */ \
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"\t"op" %2, %0, %4\n" /* Calculate new value. */ \
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"\tand %2, %5\n" /* Isolate affected part. */ \
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"\tand %3, %6, %0\n" /* Trim out affected part. */ \
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"\tor %2, %3\n" /* Put in the new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
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"=&r" (temp2) \
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: "r" (val32.v32), "r" (posmask32.v32), \
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"r" (negmask32.v32), "m" (*mem32)); \
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return (get_1(&old, mem8)); \
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}
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EMIT_ARITHMETIC_FETCH_AND_OP_1(fetch_and_add, "addu")
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EMIT_ARITHMETIC_FETCH_AND_OP_1(fetch_and_sub, "subu")
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#define EMIT_BITWISE_FETCH_AND_OP_1(name, op, idempotence) \
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uint8_t \
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__sync_##name##_1(uint8_t *mem8, uint8_t val8) \
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{ \
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uint32_t *mem32; \
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reg_t val32, old; \
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uint32_t temp; \
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\
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mem32 = round_to_word(mem8); \
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val32.v32 = idempotence ? 0xffffffff : 0x00000000; \
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put_1(&val32, mem8, val8); \
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\
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mips_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %4\n" /* Load old value. */ \
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"\t"op" %2, %3, %0\n" /* Calculate new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp) \
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: "r" (val32.v32), "m" (*mem32)); \
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return (get_1(&old, mem8)); \
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}
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EMIT_BITWISE_FETCH_AND_OP_1(fetch_and_and, "and", 1)
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EMIT_BITWISE_FETCH_AND_OP_1(fetch_and_or, "or", 0)
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EMIT_BITWISE_FETCH_AND_OP_1(fetch_and_xor, "xor", 0)
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/*
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* 16-bit routines.
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*/
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static inline void
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put_2(reg_t *r, uint16_t *offset_ptr, uint16_t val)
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{
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@ -260,112 +141,129 @@ get_2(const reg_t *r, uint16_t *offset_ptr)
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return (bytes.out);
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}
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uint16_t
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__sync_lock_test_and_set_2(uint16_t *mem16, uint16_t val16)
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{
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uint32_t *mem32;
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reg_t val32, negmask32, old;
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uint32_t temp;
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/*
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* 8-bit and 16-bit routines.
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*
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* These operations are not natively supported by the CPU, so we use
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* some shifting and bitmasking on top of the 32-bit instructions.
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*/
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mem32 = round_to_word(mem16);
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val32.v32 = 0x00000000;
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put_2(&val32, mem16, val16);
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negmask32.v32 = 0xffffffff;
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put_2(&negmask32, mem16, 0x0000);
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mips_sync();
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__asm volatile (
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"1:"
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"\tll %0, %5\n" /* Load old value. */
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"\tand %2, %4, %0\n" /* Trim out affected part. */
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"\tor %2, %3\n" /* Combine to new value. */
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"\tsc %2, %1\n" /* Attempt to store. */
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"\tbeqz %2, 1b\n" /* Spin if failed. */
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp)
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: "r" (val32.v32), "r" (negmask32.v32), "m" (*mem32));
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return (get_2(&old, mem16));
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}
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uint16_t
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__sync_val_compare_and_swap_2(uint16_t *mem16, uint16_t expected,
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uint16_t desired)
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{
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uint32_t *mem32;
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reg_t expected32, desired32, posmask32, negmask32, old;
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uint32_t temp;
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mem32 = round_to_word(mem16);
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expected32.v32 = 0x00000000;
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put_2(&expected32, mem16, expected);
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desired32.v32 = 0x00000000;
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put_2(&desired32, mem16, desired);
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posmask32.v32 = 0x00000000;
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put_2(&posmask32, mem16, 0xffff);
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negmask32.v32 = ~posmask32.v32;
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mips_sync();
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__asm volatile (
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"1:"
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"\tll %0, %7\n" /* Load old value. */
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"\tand %2, %5, %0\n" /* Isolate affected part. */
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"\tbne %2, %3, 2f\n" /* Compare to expected value. */
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"\tand %2, %6, %0\n" /* Trim out affected part. */
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"\tor %2, %4\n" /* Put in the new value. */
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"\tsc %2, %1\n" /* Attempt to store. */
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"\tbeqz %2, 1b\n" /* Spin if failed. */
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"2:"
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: "=&r" (old), "=m" (*mem32), "=&r" (temp)
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: "r" (expected32.v32), "r" (desired32.v32),
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"r" (posmask32.v32), "r" (negmask32.v32), "m" (*mem32));
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return (get_2(&old, mem16));
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}
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#define EMIT_ARITHMETIC_FETCH_AND_OP_2(name, op) \
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uint16_t \
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__sync_##name##_2(uint16_t *mem16, uint16_t val16) \
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#define EMIT_LOCK_TEST_AND_SET_N(N, uintN_t) \
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uintN_t \
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__sync_lock_test_and_set_##N(uintN_t *mem, uintN_t val) \
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{ \
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uint32_t *mem32; \
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reg_t val32, posmask32, negmask32, old; \
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reg_t val32, negmask, old; \
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uint32_t temp; \
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\
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mem32 = round_to_word(mem); \
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val32.v32 = 0x00000000; \
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put_##N(&val32, mem, val); \
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negmask.v32 = 0xffffffff; \
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put_##N(&negmask, mem, 0); \
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\
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mips_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %5\n" /* Load old value. */ \
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"\tand %2, %4, %0\n" /* Remove the old value. */ \
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"\tor %2, %3\n" /* Put in the new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp) \
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: "r" (val32.v32), "r" (negmask.v32), "m" (*mem32)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_LOCK_TEST_AND_SET_N(1, uint8_t)
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EMIT_LOCK_TEST_AND_SET_N(2, uint16_t)
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#define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
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uintN_t \
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__sync_val_compare_and_swap_##N(uintN_t *mem, uintN_t expected, \
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uintN_t desired) \
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{ \
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uint32_t *mem32; \
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reg_t expected32, desired32, posmask, negmask, old; \
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uint32_t temp; \
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\
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mem32 = round_to_word(mem); \
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expected32.v32 = 0x00000000; \
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put_##N(&expected32, mem, expected); \
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desired32.v32 = 0x00000000; \
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put_##N(&desired32, mem, desired); \
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posmask.v32 = 0x00000000; \
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put_##N(&posmask, mem, ~0); \
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negmask.v32 = ~posmask.v32; \
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\
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mips_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %7\n" /* Load old value. */ \
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"\tand %2, %5, %0\n" /* Isolate the old value. */ \
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"\tbne %2, %3, 2f\n" /* Compare to expected value. */\
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"\tand %2, %6, %0\n" /* Remove the old value. */ \
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"\tor %2, %4\n" /* Put in the new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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"2:" \
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: "=&r" (old), "=m" (*mem32), "=&r" (temp) \
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: "r" (expected32.v32), "r" (desired32.v32), \
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"r" (posmask.v32), "r" (negmask.v32), "m" (*mem32)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_VAL_COMPARE_AND_SWAP_N(1, uint8_t)
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EMIT_VAL_COMPARE_AND_SWAP_N(2, uint16_t)
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#define EMIT_ARITHMETIC_FETCH_AND_OP_N(N, uintN_t, name, op) \
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uintN_t \
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__sync_##name##_##N(uintN_t *mem, uintN_t val) \
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{ \
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uint32_t *mem32; \
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reg_t val32, posmask, negmask, old; \
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uint32_t temp1, temp2; \
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\
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mem32 = round_to_word(mem16); \
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mem32 = round_to_word(mem); \
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val32.v32 = 0x00000000; \
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put_2(&val32, mem16, val16); \
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posmask32.v32 = 0x00000000; \
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put_2(&posmask32, mem16, 0xffff); \
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negmask32.v32 = ~posmask32.v32; \
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put_##N(&val32, mem, val); \
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posmask.v32 = 0x00000000; \
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put_##N(&posmask, mem, ~0); \
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negmask.v32 = ~posmask.v32; \
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\
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mips_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %7\n" /* Load old value. */ \
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"\t"op" %2, %0, %4\n" /* Calculate new value. */ \
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"\tand %2, %5\n" /* Isolate affected part. */ \
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"\tand %3, %6, %0\n" /* Trim out affected part. */ \
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"\tor %2, %3\n" /* Combine to new value. */ \
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"\tand %2, %5\n" /* Isolate the new value. */ \
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"\tand %3, %6, %0\n" /* Remove the old value. */ \
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"\tor %2, %3\n" /* Put in the new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
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"=&r" (temp2) \
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: "r" (val32.v32), "r" (posmask32.v32), \
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"r" (negmask32.v32), "m" (*mem32)); \
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return (get_2(&old, mem16)); \
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: "r" (val32.v32), "r" (posmask.v32), \
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"r" (negmask.v32), "m" (*mem32)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_ARITHMETIC_FETCH_AND_OP_2(fetch_and_add, "addu")
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EMIT_ARITHMETIC_FETCH_AND_OP_2(fetch_and_sub, "subu")
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EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_add, "addu")
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EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_sub, "subu")
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EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_add, "addu")
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EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_sub, "subu")
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#define EMIT_BITWISE_FETCH_AND_OP_2(name, op, idempotence) \
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uint16_t \
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__sync_##name##_2(uint16_t *mem16, uint16_t val16) \
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#define EMIT_BITWISE_FETCH_AND_OP_N(N, uintN_t, name, op, idempotence) \
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uintN_t \
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__sync_##name##_##N(uintN_t *mem, uintN_t val) \
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{ \
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uint32_t *mem32; \
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reg_t val32, old; \
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uint32_t temp; \
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\
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mem32 = round_to_word(mem16); \
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mem32 = round_to_word(mem); \
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val32.v32 = idempotence ? 0xffffffff : 0x00000000; \
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put_2(&val32, mem16, val16); \
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put_##N(&val32, mem, val); \
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\
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mips_sync(); \
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__asm volatile ( \
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@ -376,12 +274,15 @@ __sync_##name##_2(uint16_t *mem16, uint16_t val16) \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp) \
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: "r" (val32.v32), "m" (*mem32)); \
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return (get_2(&old, mem16)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_BITWISE_FETCH_AND_OP_2(fetch_and_and, "and", 1)
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EMIT_BITWISE_FETCH_AND_OP_2(fetch_and_or, "or", 0)
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EMIT_BITWISE_FETCH_AND_OP_2(fetch_and_xor, "xor", 0)
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EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_and, "and", 1)
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EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_or, "or", 0)
|
||||
EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_xor, "xor", 0)
|
||||
EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_and, "and", 1)
|
||||
EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_or, "or", 0)
|
||||
EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_xor, "xor", 0)
|
||||
|
||||
/*
|
||||
* 32-bit routines.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user