booting again.
The code is a copy of the mips/mips/tick.c with minor modifications for
XLR interrupt handling. Disable mips/rmi/clock.c for now, the PIC based
timer code will be added later.
> Description of fields to fill in above: 76 columns --|
> PR: If a GNATS PR is affected by the change.
> Submitted by: If someone else sent in the change.
> Reviewed by: If someone else reviewed your modification.
> Approved by: If you needed approval for this commit.
> Obtained from: If the change is from a third party.
> MFC after: N [day[s]|week[s]|month[s]]. Request a reminder email.
> Security: Vulnerability reference (one per line) or description.
> Empty fields above will be automatically removed.
M rmi/xls_ehci.c
M rmi/clock.h
M rmi/xlr_pci.c
M rmi/perfmon.h
M rmi/uart_bus_xlr_iodi.c
M rmi/perfmon_percpu.c
M rmi/iodi.c
M rmi/pcibus.c
M rmi/perfmon_kern.c
M rmi/perfmon_xlrconfig.h
M rmi/pcibus.h
M rmi/tick.c
M rmi/xlr_boot1_console.c
M rmi/debug.h
M rmi/uart_cpu_mips_xlr.c
M rmi/xlrconfig.h
M rmi/interrupt.h
M rmi/xlr_i2c.c
M rmi/shared_structs.h
M rmi/msgring.c
M rmi/iomap.h
M rmi/ehcireg.h
M rmi/msgring.h
M rmi/shared_structs_func.h
M rmi/on_chip.c
M rmi/pic.h
M rmi/xlr_machdep.c
M rmi/ehcivar.h
M rmi/board.c
M rmi/clock.c
M rmi/shared_structs_offsets.h
M rmi/perfmon_utils.h
M rmi/board.h
M rmi/msgring_xls.c
M rmi/intr_machdep.c
