of the rxeoc handler for now. The rxeoc handler will reset the link,
and the NatSemi chip's RX FIFO will overflow on a 32-bit bus once you
start hitting it with 500Mbps or more of traffic.
Also increase the size of the RX ring to 128 descriptors (was 64).
when we get an RX_ERR interrupt rather than the nge_rxeoc() handler. The
rxeoc (end of channel) handler attempts to reinitialize the whole NIC,
which we don't want to do if we only received a bad packet.
1) Bite the bullet, and allow unaligned accesses without buffer copies
on the i386 platform. According to some tests run by Andrew Gallatin,
the buffer copy performance hit is greater than the unaligned access
performance hit (especially with jumbo frames). We still need to copy
everywhere else.
2) Enable interrupt moderation with a 100us timeout.
Submitted by: Andrew Gallatin <no longer at duke.edu>
MFC after: 1 week
Previously, I had the MODE_1000 bit in the global config register set
unconditionally, which was wrong: we have to turn it off if we have
a 10/100 link. This is now handled in the nge_miibus_statchg() routine.
Discovered by: Nathan Binkert <binkertn@eecs.umich.edu>
(Note: this commit is being done from JFK airport. :P )
something: offset into the first mbuf of the target chain before copying
the source data over.
Make drivers using m_devget() with a first argument "data - ETHER_ALIGN"
to use the offset argument to pass ETHER_ALIGN in. The way it was previously
done is potentially dangerous if the source data was at the top of a page
and the offset caused the previous page to be copied (if the
previous page has not yet been appropriately mapped).
The old `offset' argument in m_devget() is not used anywhere (it's always
0) and dates back to ~1995 (and earlier?) when support for ethernet trailers
existed. With that support gone, it was merely collecting dust.
Tested on alpha by: jlemon
Partially submitted by: jlemon
Reviewed by: jlemon
MFC after: 3 weeks
converting from the old external mbuf buffer code to the new (with the
MEXTADD() macro). Also free free list memory correctly in
foo_free_jumbo_mem() routines: grab the head of the list, then
remove it, _then_ free() it.
This fixes the memory corruption problem I've been chasing in the level 1
driver.
The DP83820/83821 has an undocumented limitation concerning jumbo frames
and TX checksum offload. In order for TX checksum offload to work, the
outgoing frame must fit entirely within the TX FIFO, which is 8192 bytes
in size. This isn't a problem, until you try to send a 9000-byte frame,
at which point the TX DMA engine goes to sleep. It turns out that if
you want to send a jumbo frame larger than 8170 bytes (8192 - 64), you
have to turn off the TX checksum support.
As a workaround, I changed nge_ioctl() so that if the user selects an
MTU larger than 8152 bytes, we clear the if_hwassist flags. The flags
will be set again once the MTU is reduced to a smaller value.
we want the checksums calculated on a per-packet basis using control bits
in the extsts field of the DMA descriptor structure. For TX, the chip
seems to want these bits set in the field of the first descriptor in
a fragment chain, not the last.
use of the extsts field in DMA descriptors. We need this to tell the chip
to calculate TCP/IP checksums in hardware on a per-packet basis.
- Fix the unions in DMA descriptor structures. Breakage on alpha led
me to realize I'd done it wrong the first time.
UDP checksums too, not just IP. The chip only tells us if the checksum
is ok, it does not give us a copy of the partial checksum for later
processing. We have to deal with this the right way, but we can deal
with it.
be unions with enough padding to make sure they always end up being
a multiple of 8 bytes in size, since the 83820/83821 chips require
descriptors to be aligned on 64-bit boundaries. I happened to get it
right for the 32-bit descriptor/x86 case, but botched everything else.
Things should work properle on 32-bit/64-bit platforms now.
Note that the 64-bit descriptor format isn't being used currently.
and DP83821 gigabit ethernet MAC chips and the NatSemi DP83861 10/100/1000
copper PHY. There are a whole bunch of very low cost cards available with
this chipset selling for $150USD or less. This includes the SMC9462TX,
D-Link DGE-500T, Asante GigaNIX 1000TA and 1000TPC, and a couple cards
from Addtron.
This chip supports TCP/IP checksum offload, VLAN tagging/insertion.
2048-bit multicast filter, jumbograms and has 8K TX and 32K RX FIFOs.
I have not done serious performance testing with this driver. I know
it works, and I want it under CVS control so I can keep tabs on it.
Note that there's no serious mutex stuff in here yet either: I need
to talk more with jhb to figure out the right way to do this. That
said, I don't think there will be any problems.
This driver should also work on the alpha. It's not turned on in
GENERIC.
