for an interrupt to enable/disable from the vector (and GID too, if we
had multiple GIDs)- so, stupidly for now, search for the right mcpcia's
softc so we have the right base address for the bridge CSR to apply
IRQ bit-twiddle's to. Alas- this doesn't yet allow us to run, but it's
the right direction.
- Make softinterrupts (SWI's) almost completely MI, and divorce them
completely from the x86 hardware interrupt code.
- The ihandlers array is now gone. Instead, there is a MI shandlers array
that just contains SWI handlers.
- Most of the former machine/ipl.h files have moved to a new sys/ipl.h.
- Stub out all the spl*() functions on all architectures.
Submitted by: dfr
the drivers.
* Remove legacy inx/outx support from chipset and replace with macros
which call busspace.
* Rework pci config accesses to route through the pcib device instead of
calling a MD function directly.
With these changes it is possible to cleanly support machines which have
more than one independantly numbered PCI busses. As a bonus, the new
busspace implementation should be measurably faster than the old one.
hose are 16 PCI instances apart. This allows us to recognize secondary
PCI busses (at least to a first level) until the pci infrastructure is
fixed.
Turn on support for secondary cycles, too. Redo debug printouts.
like to see the true SRM bus number be passed to us, instead, we get FreeBSD's
PCI bus instance number (Brzzt! Wrong Answer!).
Also, once we've seen the MCPCIA that has the EISA bus on it, call
dec_kn300_cons_init just before configuring devices on this bus.
